3 files changed, 16 insertions, 16 deletions

diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 5bfc3b29f..82dac6aa9 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -114,10 +114,10 @@ class MinorCPU : public BaseCPU
 
   protected:
      /** Return a reference to the data port. */
-    MasterPort &getDataPort();
+    MasterPort &getDataPort() override;
 
     /** Return a reference to the instruction port. */
-    MasterPort &getInstPort();
+    MasterPort &getInstPort() override;
 
   public:
     MinorCPU(MinorCPUParams *params);
@@ -126,8 +126,8 @@ class MinorCPU : public BaseCPU
 
   public:
     /** Starting, waking and initialisation */
-    void init();
-    void startup();
+    void init() override;
+    void startup() override;
     void wakeup(ThreadID tid) override;
 
     Addr dbg_vtophys(Addr addr);
@@ -136,18 +136,18 @@ class MinorCPU : public BaseCPU
     Minor::MinorStats stats;
 
     /** Stats interface from SimObject (by way of BaseCPU) */
-    void regStats();
+    void regStats() override;
 
     /** Simple inst count interface from BaseCPU */
-    Counter totalInsts() const;
-    Counter totalOps() const;
+    Counter totalInsts() const override;
+    Counter totalOps() const override;
 
     void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
     void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 
     /** Serialize pipeline data */
-    void serialize(CheckpointOut &cp) const;
-    void unserialize(CheckpointIn &cp);
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
 
     /** Drain interface */
     DrainState drain() override;
@@ -155,15 +155,15 @@ class MinorCPU : public BaseCPU
     /** Signal from Pipeline that MinorCPU should signal that a drain
      *  is complete and set its drainState */
     void signalDrainDone();
-    void memWriteback();
+    void memWriteback() override;
 
     /** Switching interface from BaseCPU */
-    void switchOut();
-    void takeOverFrom(BaseCPU *old_cpu);
+    void switchOut() override;
+    void takeOverFrom(BaseCPU *old_cpu) override;
 
     /** Thread activation interface from BaseCPU. */
-    void activateContext(ThreadID thread_id);
-    void suspendContext(ThreadID thread_id);
+    void activateContext(ThreadID thread_id) override;
+    void suspendContext(ThreadID thread_id) override;
 
     /** Interface for stages to signal that they have become active after
      *  a callback or eventq event where the pipeline itself may have
diff --git a/src/cpu/minor/func_unit.cc b/src/cpu/minor/func_unit.cc
index 65dd1eefc..aeee5cc44 100644
--- a/src/cpu/minor/func_unit.cc
+++ b/src/cpu/minor/func_unit.cc
@@ -223,7 +223,7 @@ FUPipeline::findTiming(const StaticInstPtr &inst)
                 "Found extra timing match (pattern %d '%s')"
                 " %s %16x (type %s)\n",
                 i, timing.description, inst->disassemble(0), mach_inst,
-                typeid(*inst).name());
+                typeid(inst).name());
 
             return &timing;
         }
diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh
index 213def58e..2e1aa9921 100644
--- a/src/cpu/minor/pipeline.hh
+++ b/src/cpu/minor/pipeline.hh
@@ -124,7 +124,7 @@ class Pipeline : public Ticked
 
     /** A custom evaluate allows report in the right place (between
      *  stages and pipeline advance) */
-    void evaluate();
+    void evaluate() override;
 
     void countCycles(Cycles delta) override
     {