diff options
Diffstat (limited to 'src/cpu/minor')
| -rw-r--r-- | src/cpu/minor/dyn_inst.cc | 14 | ||||
| -rw-r--r-- | src/cpu/minor/exec_context.hh | 84 | ||||
| -rw-r--r-- | src/cpu/minor/scoreboard.cc | 36 | ||||
| -rw-r--r-- | src/cpu/minor/scoreboard.hh | 2 |
4 files changed, 59 insertions, 77 deletions
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc index 42c370a70..1ed598833 100644 --- a/src/cpu/minor/dyn_inst.cc +++ b/src/cpu/minor/dyn_inst.cc @@ -133,15 +133,13 @@ operator <<(std::ostream &os, const MinorDynInst &inst) /** Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer, * float, misc and zero registers given an 'architectural register number' */ static void -printRegName(std::ostream &os, RegId reg) +printRegName(std::ostream &os, const RegId& reg) { - RegClass reg_class = reg.regClass; - - switch (reg_class) + switch (reg.classValue()) { case MiscRegClass: { - RegIndex misc_reg = reg.regIdx; + RegIndex misc_reg = reg.index(); /* This is an ugly test because not all archs. have miscRegName */ #if THE_ISA == ARM_ISA @@ -153,17 +151,17 @@ printRegName(std::ostream &os, RegId reg) } break; case FloatRegClass: - os << 'f' << static_cast<unsigned int>(reg.regIdx); + os << 'f' << static_cast<unsigned int>(reg.index()); break; case IntRegClass: if (reg.isZeroReg()) { os << 'z'; } else { - os << 'r' << static_cast<unsigned int>(reg.regIdx); + os << 'r' << static_cast<unsigned int>(reg.index()); } break; case CCRegClass: - os << 'c' << static_cast<unsigned int>(reg.regIdx); + os << 'c' << static_cast<unsigned int>(reg.index()); } } diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index d517d5abb..e91b7a6dd 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -124,51 +124,51 @@ class ExecContext : public ::ExecContext IntReg readIntRegOperand(const StaticInst *si, int idx) override { - RegId reg = si->srcRegIdx(idx); - assert(reg.regClass == IntRegClass); - return thread.readIntReg(reg.regIdx); + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isIntReg()); + return thread.readIntReg(reg.index()); } TheISA::FloatReg readFloatRegOperand(const StaticInst *si, int idx) override { - RegId reg = si->srcRegIdx(idx); - assert(reg.regClass == FloatRegClass); - return thread.readFloatReg(reg.regIdx); + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isFloatReg()); + return thread.readFloatReg(reg.index()); } TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override { - RegId reg = si->srcRegIdx(idx); - assert(reg.regClass == FloatRegClass); - return thread.readFloatRegBits(reg.regIdx); + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isFloatReg()); + return thread.readFloatRegBits(reg.index()); } void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override { - RegId reg = si->destRegIdx(idx); - assert(reg.regClass == IntRegClass); - thread.setIntReg(reg.regIdx, val); + const RegId& reg = si->destRegIdx(idx); + assert(reg.isIntReg()); + thread.setIntReg(reg.index(), val); } void setFloatRegOperand(const StaticInst *si, int idx, TheISA::FloatReg val) override { - RegId reg = si->destRegIdx(idx); - assert(reg.regClass == FloatRegClass); - thread.setFloatReg(reg.regIdx, val); + const RegId& reg = si->destRegIdx(idx); + assert(reg.isFloatReg()); + thread.setFloatReg(reg.index(), val); } void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val) override { - RegId reg = si->destRegIdx(idx); - assert(reg.regClass == FloatRegClass); - thread.setFloatRegBits(reg.regIdx, val); + const RegId& reg = si->destRegIdx(idx); + assert(reg.isFloatReg()); + thread.setFloatRegBits(reg.index(), val); } bool @@ -216,18 +216,18 @@ class ExecContext : public ::ExecContext TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) override { - RegId reg = si->srcRegIdx(idx); - assert(reg.regClass == MiscRegClass); - return thread.readMiscReg(reg.regIdx); + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isMiscReg()); + return thread.readMiscReg(reg.index()); } void setMiscRegOperand(const StaticInst *si, int idx, const TheISA::MiscReg &val) override { - RegId reg = si->destRegIdx(idx); - assert(reg.regClass == MiscRegClass); - return thread.setMiscReg(reg.regIdx, val); + const RegId& reg = si->destRegIdx(idx); + assert(reg.isMiscReg()); + return thread.setMiscReg(reg.index(), val); } Fault @@ -279,17 +279,17 @@ class ExecContext : public ::ExecContext TheISA::CCReg readCCRegOperand(const StaticInst *si, int idx) override { - RegId reg = si->srcRegIdx(idx); - assert(reg.regClass == CCRegClass); - return thread.readCCReg(reg.regIdx); + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isCCReg()); + return thread.readCCReg(reg.index()); } void setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override { - RegId reg = si->destRegIdx(idx); - assert(reg.regClass == CCRegClass); - thread.setCCReg(reg.regIdx, val); + const RegId& reg = si->destRegIdx(idx); + assert(reg.isCCReg()); + thread.setCCReg(reg.index(), val); } void @@ -320,46 +320,46 @@ class ExecContext : public ::ExecContext /* MIPS: other thread register reading/writing */ uint64_t - readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID) + readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID) { SimpleThread *other_thread = (tid == InvalidThreadID ? &thread : cpu.threads[tid]); - switch(reg.regClass) { + switch (reg.classValue()) { case IntRegClass: - return other_thread->readIntReg(reg.regIdx); + return other_thread->readIntReg(reg.index()); break; case FloatRegClass: - return other_thread->readFloatRegBits(reg.regIdx); + return other_thread->readFloatRegBits(reg.index()); break; case MiscRegClass: - return other_thread->readMiscReg(reg.regIdx); + return other_thread->readMiscReg(reg.index()); default: panic("Unexpected reg class! (%s)", - RegClassStrings[reg.regClass]); + reg.className()); return 0; } } void - setRegOtherThread(RegId reg, const TheISA::MiscReg &val, + setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val, ThreadID tid = InvalidThreadID) { SimpleThread *other_thread = (tid == InvalidThreadID ? &thread : cpu.threads[tid]); - switch(reg.regClass) { + switch (reg.classValue()) { case IntRegClass: - return other_thread->setIntReg(reg.regIdx, val); + return other_thread->setIntReg(reg.index(), val); break; case FloatRegClass: - return other_thread->setFloatRegBits(reg.regIdx, val); + return other_thread->setFloatRegBits(reg.index(), val); break; case MiscRegClass: - return other_thread->setMiscReg(reg.regIdx, val); + return other_thread->setMiscReg(reg.index(), val); default: panic("Unexpected reg class! (%s)", - RegClassStrings[reg.regClass]); + reg.className()); } } diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc index 31657b310..e3497a5cf 100644 --- a/src/cpu/minor/scoreboard.cc +++ b/src/cpu/minor/scoreboard.cc @@ -48,7 +48,7 @@ namespace Minor { bool -Scoreboard::findIndex(RegId reg, Index &scoreboard_index) +Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index) { bool ret = false; @@ -56,19 +56,19 @@ Scoreboard::findIndex(RegId reg, Index &scoreboard_index) /* Don't bother with the zero register */ ret = false; } else { - switch (reg.regClass) + switch (reg.classValue()) { case IntRegClass: - scoreboard_index = reg.regIdx; + scoreboard_index = reg.index(); ret = true; break; case FloatRegClass: scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + - reg.regIdx; + reg.index(); ret = true; break; case CCRegClass: - scoreboard_index = TheISA::NumIntRegs + reg.regIdx; + scoreboard_index = TheISA::NumIntRegs + reg.index(); ret = true; break; case MiscRegClass: @@ -83,26 +83,9 @@ Scoreboard::findIndex(RegId reg, Index &scoreboard_index) /** Flatten a RegId, irrespective of what reg type it's pointing to */ static RegId -flattenRegIndex(RegId reg, ThreadContext *thread_context) +flattenRegIndex(const RegId& reg, ThreadContext *thread_context) { - switch (reg.regClass) - { - case IntRegClass: - reg.regIdx = thread_context->flattenIntIndex(reg.regIdx); - break; - case FloatRegClass: - reg.regIdx = thread_context->flattenFloatIndex(reg.regIdx); - break; - case CCRegClass: - reg.regIdx = thread_context->flattenCCIndex(reg.regIdx); - break; - case MiscRegClass: - /* Don't bother to flatten misc regs as we don't need them here */ - /* return thread_context->flattenMiscIndex(reg); */ - break; - } - - return reg; + return thread_context->flattenRegId(reg); } void @@ -143,7 +126,8 @@ Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time, *inst, index, numResults[index], returnCycle[index]); } else { /* Use ZeroReg to mark invalid/untracked dests */ - inst->flatDestRegIdx[dest_index] = RegId::zeroReg; + inst->flatDestRegIdx[dest_index] = RegId(IntRegClass, + TheISA::ZeroReg); } } } @@ -190,7 +174,7 @@ Scoreboard::clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable) for (unsigned int dest_index = 0; dest_index < num_dests; dest_index++) { - RegId reg = inst->flatDestRegIdx[dest_index]; + const RegId& reg = inst->flatDestRegIdx[dest_index]; Index index; if (findIndex(reg, index)) { diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh index 815d81408..7fe5002f9 100644 --- a/src/cpu/minor/scoreboard.hh +++ b/src/cpu/minor/scoreboard.hh @@ -106,7 +106,7 @@ class Scoreboard : public Named /** Sets scoreboard_index to the index into numResults of the * given register index. Returns true if the given register * is in the scoreboard and false if it isn't */ - bool findIndex(RegId reg, Index &scoreboard_index); + bool findIndex(const RegId& reg, Index &scoreboard_index); /** Mark up an instruction's effects by incrementing * numResults counts. If mark_unpredictable is true, the inst's |