diff options
Diffstat (limited to 'src/cpu/minor')
-rw-r--r-- | src/cpu/minor/dyn_inst.cc | 11 | ||||
-rw-r--r-- | src/cpu/minor/exec_context.hh | 122 | ||||
-rw-r--r-- | src/cpu/minor/scoreboard.cc | 15 | ||||
-rw-r--r-- | src/cpu/minor/scoreboard.hh | 4 |
4 files changed, 147 insertions, 5 deletions
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc index 1ed598833..756b214bd 100644 --- a/src/cpu/minor/dyn_inst.cc +++ b/src/cpu/minor/dyn_inst.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 ARM Limited + * Copyright (c) 2013-2014, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -153,6 +153,13 @@ printRegName(std::ostream &os, const RegId& reg) case FloatRegClass: os << 'f' << static_cast<unsigned int>(reg.index()); break; + case VecRegClass: + os << 'v' << static_cast<unsigned int>(reg.index()); + break; + case VecElemClass: + os << 'v' << static_cast<unsigned int>(reg.index()) << '[' << + static_cast<unsigned int>(reg.elemIndex()) << ']'; + break; case IntRegClass: if (reg.isZeroReg()) { os << 'z'; @@ -162,6 +169,8 @@ printRegName(std::ostream &os, const RegId& reg) break; case CCRegClass: os << 'c' << static_cast<unsigned int>(reg.index()); + default: + panic("Unknown register class: %d", (int)reg.classValue()); } } diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index e91b7a6dd..4b3a02fca 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2014 ARM Limited + * Copyright (c) 2011-2014, 2016 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -145,6 +145,30 @@ class ExecContext : public ::ExecContext return thread.readFloatRegBits(reg.index()); } + const TheISA::VecRegContainer& + readVecRegOperand(const StaticInst *si, int idx) const override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecReg()); + return thread.readVecReg(reg); + } + + TheISA::VecRegContainer& + getWritableVecRegOperand(const StaticInst *si, int idx) override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread.getWritableVecReg(reg); + } + + TheISA::VecElem + readVecElemOperand(const StaticInst *si, int idx) const override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecReg()); + return thread.readVecElem(reg); + } + void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override { @@ -171,6 +195,102 @@ class ExecContext : public ::ExecContext thread.setFloatRegBits(reg.index(), val); } + void + setVecRegOperand(const StaticInst *si, int idx, + const TheISA::VecRegContainer& val) override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + thread.setVecReg(reg, val); + } + + /** Vector Register Lane Interfaces. */ + /** @{ */ + /** Reads source vector 8bit operand. */ + ConstVecLane8 + readVec8BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecReg()); + return thread.readVec8BitLaneReg(reg); + } + + /** Reads source vector 16bit operand. */ + ConstVecLane16 + readVec16BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecReg()); + return thread.readVec16BitLaneReg(reg); + } + + /** Reads source vector 32bit operand. */ + ConstVecLane32 + readVec32BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecReg()); + return thread.readVec32BitLaneReg(reg); + } + + /** Reads source vector 64bit operand. */ + ConstVecLane64 + readVec64BitLaneOperand(const StaticInst *si, int idx) const + override + { + const RegId& reg = si->srcRegIdx(idx); + assert(reg.isVecReg()); + return thread.readVec64BitLaneReg(reg); + } + + /** Write a lane of the destination vector operand. */ + template <typename LD> + void + setVecLaneOperandT(const StaticInst *si, int idx, + const LD& val) + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + return thread.setVecLane(reg, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData<LaneSize::Byte>& val) override + { + setVecLaneOperandT(si, idx, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData<LaneSize::TwoByte>& val) override + { + setVecLaneOperandT(si, idx, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData<LaneSize::FourByte>& val) override + { + setVecLaneOperandT(si, idx, val); + } + virtual void + setVecLaneOperand(const StaticInst *si, int idx, + const LaneData<LaneSize::EightByte>& val) override + { + setVecLaneOperandT(si, idx, val); + } + /** @} */ + + void + setVecElemOperand(const StaticInst *si, int idx, + const TheISA::VecElem val) override + { + const RegId& reg = si->destRegIdx(idx); + assert(reg.isVecReg()); + thread.setVecElem(reg, val); + } + bool readPredicate() override { diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc index e3497a5cf..c56d3b303 100644 --- a/src/cpu/minor/scoreboard.cc +++ b/src/cpu/minor/scoreboard.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 ARM Limited + * Copyright (c) 2013-2014, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -67,6 +67,16 @@ Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index) reg.index(); ret = true; break; + case VecRegClass: + scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + + TheISA::NumFloatRegs + reg.index(); + ret = true; + break; + case VecElemClass: + scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + + TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index(); + ret = true; + break; case CCRegClass: scoreboard_index = TheISA::NumIntRegs + reg.index(); ret = true; @@ -75,6 +85,9 @@ Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index) /* Don't bother with Misc registers */ ret = false; break; + default: + panic("Unknown register class: %d", + static_cast<int>(reg.classValue())); } } diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh index 7fe5002f9..9e42c2a6b 100644 --- a/src/cpu/minor/scoreboard.hh +++ b/src/cpu/minor/scoreboard.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 ARM Limited + * Copyright (c) 2013-2014, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -94,7 +94,7 @@ class Scoreboard : public Named Scoreboard(const std::string &name) : Named(name), numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs + - TheISA::NumFloatRegs), + TheISA::NumFloatRegs + TheISA::NumVecRegs), numResults(numRegs, 0), numUnpredictableResults(numRegs, 0), fuIndices(numRegs, 0), |