1 files changed, 1 insertions, 18 deletions
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 238d11352..19bae74bf 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -99,7 +99,7 @@ class ExecContext : public ::ExecContext
         setPredicate(true);
         thread.setIntReg(TheISA::ZeroReg, 0);
 #if THE_ISA == ALPHA_ISA
-        thread.setFloatReg(TheISA::ZeroReg, 0.0);
+        thread.setFloatRegBits(TheISA::ZeroReg, 0);
 #endif
     }
 
@@ -129,14 +129,6 @@ class ExecContext : public ::ExecContext
         return thread.readIntReg(reg.index());
     }
 
-    TheISA::FloatReg
-    readFloatRegOperand(const StaticInst *si, int idx) override
-    {
-        const RegId& reg = si->srcRegIdx(idx);
-        assert(reg.isFloatReg());
-        return thread.readFloatReg(reg.index());
-    }
-
     TheISA::FloatRegBits
     readFloatRegOperandBits(const StaticInst *si, int idx) override
     {
@@ -178,15 +170,6 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setFloatRegOperand(const StaticInst *si, int idx,
-        TheISA::FloatReg val) override
-    {
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isFloatReg());
-        thread.setFloatReg(reg.index(), val);
-    }
-
-    void
     setFloatRegOperandBits(const StaticInst *si, int idx,
         TheISA::FloatRegBits val) override
     {