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-rw-r--r--src/cpu/o3/FuncUnitConfig.py35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index 954381f86..34c56163d 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2010 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -51,6 +63,29 @@ class FP_MultDiv(FUDesc):
OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
count = 2
+class SIMD_Unit(FUDesc):
+ opList = [ OpDesc(opClass='SimdAdd'),
+ OpDesc(opClass='SimdAddAcc'),
+ OpDesc(opClass='SimdAlu'),
+ OpDesc(opClass='SimdCmp'),
+ OpDesc(opClass='SimdCvt'),
+ OpDesc(opClass='SimdMisc'),
+ OpDesc(opClass='SimdMult'),
+ OpDesc(opClass='SimdMultAcc'),
+ OpDesc(opClass='SimdShift'),
+ OpDesc(opClass='SimdShiftAcc'),
+ OpDesc(opClass='SimdSqrt'),
+ OpDesc(opClass='SimdFloatAdd'),
+ OpDesc(opClass='SimdFloatAlu'),
+ OpDesc(opClass='SimdFloatCmp'),
+ OpDesc(opClass='SimdFloatCvt'),
+ OpDesc(opClass='SimdFloatDiv'),
+ OpDesc(opClass='SimdFloatMisc'),
+ OpDesc(opClass='SimdFloatMult'),
+ OpDesc(opClass='SimdFloatMultAcc'),
+ OpDesc(opClass='SimdFloatSqrt') ]
+ count = 4
+
class ReadPort(FUDesc):
opList = [ OpDesc(opClass='MemRead') ]
count = 0