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Diffstat (limited to 'src/cpu/o3/FuncUnitConfig.py')
| -rw-r--r-- | src/cpu/o3/FuncUnitConfig.py | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py index ef114df09..3b02aab79 100644 --- a/src/cpu/o3/FuncUnitConfig.py +++ b/src/cpu/o3/FuncUnitConfig.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010 ARM Limited +# Copyright (c) 2010, 2017 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -86,6 +86,7 @@ class SIMD_Unit(FUDesc): OpDesc(opClass='SimdMultAcc'), OpDesc(opClass='SimdShift'), OpDesc(opClass='SimdShiftAcc'), + OpDesc(opClass='SimdDiv'), OpDesc(opClass='SimdSqrt'), OpDesc(opClass='SimdFloatAdd'), OpDesc(opClass='SimdFloatAlu'), @@ -95,9 +96,18 @@ class SIMD_Unit(FUDesc): OpDesc(opClass='SimdFloatMisc'), OpDesc(opClass='SimdFloatMult'), OpDesc(opClass='SimdFloatMultAcc'), - OpDesc(opClass='SimdFloatSqrt') ] + OpDesc(opClass='SimdFloatSqrt'), + OpDesc(opClass='SimdReduceAdd'), + OpDesc(opClass='SimdReduceAlu'), + OpDesc(opClass='SimdReduceCmp'), + OpDesc(opClass='SimdFloatReduceAdd'), + OpDesc(opClass='SimdFloatReduceCmp') ] count = 4 +class PredALU(FUDesc): + opList = [ OpDesc(opClass='SimdPredAlu') ] + count = 1 + class ReadPort(FUDesc): opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='FloatMemRead') ] |