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-rw-r--r--src/cpu/o3/FuncUnitConfig.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index f0c70f55a..ef114df09 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -41,7 +41,8 @@
from m5.SimObject import SimObject
from m5.defines import buildEnv
from m5.params import *
-from FuncUnit import *
+
+from m5.objects.FuncUnit import *
class IntALU(FUDesc):
opList = [ OpDesc(opClass='IntAlu') ]