summaryrefslogtreecommitdiff
path: root/src/cpu/o3/O3CPU.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
-rw-r--r--src/cpu/o3/O3CPU.py3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 1d8950a73..ffc817e81 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -49,9 +49,6 @@ class DerivO3CPU(BaseCPU):
checker.dtb = Parent.dtb
cachePorts = Param.Unsigned(200, "Cache Ports")
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
- _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port']
decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")