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-rw-r--r--src/cpu/o3/O3CPU.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e691cfe5d..27ca8ce1e 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -52,8 +52,8 @@ class DerivO3CPU(BaseCPU):
else:
checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
warnOnlyOnLoadError=False), "checker")
- checker.itb = Parent.itb
- checker.dtb = Parent.dtb
+ checker.itb = Parent.itb
+ checker.dtb = Parent.dtb
cachePorts = Param.Unsigned(200, "Cache Ports")
icache_port = Port("Instruction Port")