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-rw-r--r--src/cpu/o3/O3CPU.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 8e17d9a3f..4a994f07f 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -77,7 +77,9 @@ class DerivO3CPU(BaseCPU):
activity = Param.Unsigned(0, "Initial count")
cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
- "Constrains stores only. Loads are constrained by load FUs.")
+ "Constrains stores only.")
+ cacheLoadPorts = Param.Unsigned(200, "Cache Ports. "
+ "Constrains loads only.")
decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")