summaryrefslogtreecommitdiff
path: root/src/cpu/o3/O3CPU.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
-rw-r--r--src/cpu/o3/O3CPU.py11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e73c09334..8e17d9a3f 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -43,10 +43,11 @@ from __future__ import print_function
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
-from BaseCPU import BaseCPU
-from FUPool import *
-from O3Checker import O3Checker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.FUPool import *
+from m5.objects.O3Checker import O3Checker
+from m5.objects.BranchPredictor import *
class FetchPolicy(ScopedEnum):
vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
@@ -178,7 +179,7 @@ class DerivO3CPU(BaseCPU):
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
- from ArmTLB import ArmTLB
+ from m5.objects.ArmTLB import ArmTLB
self.checker = O3Checker(workload=self.workload,
exitOnError=False,