diff options
Diffstat (limited to 'src/cpu/o3/alpha/cpu.hh')
| -rw-r--r-- | src/cpu/o3/alpha/cpu.hh | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 474fce02a..01749a2a2 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -37,6 +37,12 @@ #include "cpu/o3/cpu.hh" #include "sim/byteswap.hh" +namespace TheISA +{ + class ITB; + class DTB; +} + class EndQuiesceEvent; namespace Kernel { class Statistics; @@ -73,9 +79,9 @@ class AlphaO3CPU : public FullO3CPU<Impl> #if FULL_SYSTEM /** ITB pointer. */ - AlphaITB *itb; + AlphaISA::ITB *itb; /** DTB pointer. */ - AlphaDTB *dtb; + AlphaISA::DTB *dtb; #endif /** Registers statistics. */ @@ -126,15 +132,15 @@ class AlphaO3CPU : public FullO3CPU<Impl> /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid); + MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given * thread. The source of the squash is an external update of |