6 files changed, 32 insertions, 25 deletions

diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 474fce02a..01749a2a2 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -37,6 +37,12 @@
 #include "cpu/o3/cpu.hh"
 #include "sim/byteswap.hh"
 
+namespace TheISA
+{
+    class ITB;
+    class DTB;
+}
+
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
@@ -73,9 +79,9 @@ class AlphaO3CPU : public FullO3CPU<Impl>
 
 #if FULL_SYSTEM
     /** ITB pointer. */
-    AlphaITB *itb;
+    AlphaISA::ITB *itb;
     /** DTB pointer. */
-    AlphaDTB *dtb;
+    AlphaISA::DTB *dtb;
 #endif
 
     /** Registers statistics. */
@@ -126,15 +132,15 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
+    MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
+    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
      * thread.  The source of the squash is an external update of
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index ff123a6f7..a00dd5005 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -54,8 +54,8 @@ Param<int> activity;
 #if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<AlphaISA::ITB *> itb;
+SimObjectParam<AlphaISA::DTB *> dtb;
 Param<Tick> profile;
 #else
 SimObjectVectorParam<Process *> workload;
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index a57c5d9ed..7f10e43c2 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -198,25 +198,24 @@ AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 
 template <class Impl>
 TheISA::MiscReg
-AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
-                                        unsigned tid)
+AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
+    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
 }
 
 template <class Impl>
-Fault
+void
 AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
 {
-    return this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
-Fault
+void
 AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
                                        unsigned tid)
 {
-    return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 31a6f7753..e711de510 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -102,14 +102,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, fault,
-                                                this->threadNumber);
+        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
         return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
@@ -118,7 +117,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         return this->cpu->setMiscRegWithEffect(misc_reg, val,
                                                this->threadNumber);
diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh
index c618cee08..b6b84b2a1 100644
--- a/src/cpu/o3/alpha/params.hh
+++ b/src/cpu/o3/alpha/params.hh
@@ -35,8 +35,11 @@
 #include "cpu/o3/params.hh"
 
 //Forward declarations
-class AlphaDTB;
-class AlphaITB;
+namespace AlphaISA
+{
+    class DTB;
+    class ITB;
+}
 class MemObject;
 class Process;
 class System;
@@ -52,8 +55,8 @@ class AlphaSimpleParams : public O3Params
   public:
 
 #if FULL_SYSTEM
-    AlphaITB *itb;
-    AlphaDTB *dtb;
+    AlphaISA::ITB *itb;
+    AlphaISA::DTB *dtb;
 #endif
 };
 
diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh
index 70a09940f..f0cecee35 100644
--- a/src/cpu/o3/alpha/thread_context.hh
+++ b/src/cpu/o3/alpha/thread_context.hh
@@ -37,10 +37,10 @@ class AlphaTC : public O3ThreadContext<Impl>
   public:
 #if FULL_SYSTEM
     /** Returns a pointer to the ITB. */
-    virtual AlphaITB *getITBPtr() { return this->cpu->itb; }
+    virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; }
 
     /** Returns a pointer to the DTB. */
-    virtual AlphaDTB *getDTBPtr() { return this->cpu->dtb; }
+    virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; }
 
     /** Returns pointer to the quiesce event. */
     virtual EndQuiesceEvent *getQuiesceEvent()