diff options
Diffstat (limited to 'src/cpu/o3/alpha_cpu.hh')
| -rw-r--r-- | src/cpu/o3/alpha_cpu.hh | 105 |
1 files changed, 93 insertions, 12 deletions
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh index 4d889866a..2e5c856a8 100644 --- a/src/cpu/o3/alpha_cpu.hh +++ b/src/cpu/o3/alpha_cpu.hh @@ -43,6 +43,14 @@ namespace Kernel { class TranslatingPort; +/** + * AlphaFullCPU class. Derives from the FullO3CPU class, and + * implements all ISA and implementation specific functions of the + * CPU. This is the CPU class that is used for the SimObjects, and is + * what is given to the DynInsts. Most of its state exists in the + * FullO3CPU; the state is has is mainly for ISA specific + * functionality. + */ template <class Impl> class AlphaFullCPU : public FullO3CPU<Impl> { @@ -62,83 +70,120 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Constructs an AlphaFullCPU with the given parameters. */ AlphaFullCPU(Params *params); + /** + * Derived ExecContext class for use with the AlphaFullCPU. It + * provides the interface for any external objects to access a + * single thread's state and some general CPU state. Any time + * external objects try to update state through this interface, + * the CPU will create an event to squash all in-flight + * instructions in order to ensure state is maintained correctly. + */ class AlphaXC : public ExecContext { public: + /** Pointer to the CPU. */ AlphaFullCPU<Impl> *cpu; + /** Pointer to the thread state that this XC corrseponds to. */ O3ThreadState<Impl> *thread; + /** Returns a pointer to this CPU. */ virtual BaseCPU *getCpuPtr() { return cpu; } + /** Sets this CPU's ID. */ virtual void setCpuId(int id) { cpu->cpu_id = id; } + /** Reads this CPU's ID. */ virtual int readCpuId() { return cpu->cpu_id; } virtual TranslatingPort *getMemPort() { return /*thread->port*/ NULL; } #if FULL_SYSTEM + /** Returns a pointer to the system. */ virtual System *getSystemPtr() { return cpu->system; } + /** Returns a pointer to physical memory. */ virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } + /** Returns a pointer to the ITB. */ virtual AlphaITB *getITBPtr() { return cpu->itb; } - virtual AlphaDTB * getDTBPtr() { return cpu->dtb; } + /** Returns a pointer to the DTB. */ + virtual AlphaDTB *getDTBPtr() { return cpu->dtb; } + /** Returns a pointer to this thread's kernel statistics. */ virtual Kernel::Statistics *getKernelStats() { return thread->kernelStats; } #else + /** Returns a pointer to this thread's process. */ virtual Process *getProcessPtr() { return thread->process; } #endif - + /** Returns this thread's status. */ virtual Status status() const { return thread->status(); } + /** Sets this thread's status. */ virtual void setStatus(Status new_status) { thread->setStatus(new_status); } - /// Set the status to Active. Optional delay indicates number of - /// cycles to wait before beginning execution. + /** Set the status to Active. Optional delay indicates number of + * cycles to wait before beginning execution. */ virtual void activate(int delay = 1); - /// Set the status to Suspended. + /** Set the status to Suspended. */ virtual void suspend(); - /// Set the status to Unallocated. + /** Set the status to Unallocated. */ virtual void deallocate(); - /// Set the status to Halted. + /** Set the status to Halted. */ virtual void halt(); #if FULL_SYSTEM + /** Dumps the function profiling information. + * @todo: Implement. + */ virtual void dumpFuncProfile(); #endif - + /** Takes over execution of a thread from another CPU. */ virtual void takeOverFrom(ExecContext *old_context); + /** Registers statistics associated with this XC. */ virtual void regStats(const std::string &name); + /** Serializes state. */ virtual void serialize(std::ostream &os); + /** Unserializes state. */ virtual void unserialize(Checkpoint *cp, const std::string §ion); #if FULL_SYSTEM + /** Returns pointer to the quiesce event. */ virtual EndQuiesceEvent *getQuiesceEvent(); + /** Reads the last tick that this thread was activated on. */ virtual Tick readLastActivate(); + /** Reads the last tick that this thread was suspended on. */ virtual Tick readLastSuspend(); + /** Clears the function profiling information. */ virtual void profileClear(); + /** Samples the function profiling information. */ virtual void profileSample(); #endif - + /** Returns this thread's ID number. */ virtual int getThreadNum() { return thread->tid; } + /** Returns the instruction this thread is currently committing. + * Only used when an instruction faults. + */ virtual TheISA::MachInst getInst(); + /** Copies the architectural registers from another XC into this XC. */ virtual void copyArchRegs(ExecContext *xc); + /** Resets all architectural registers to 0. */ virtual void clearArchRegs(); + /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); virtual FloatReg readFloatReg(int reg_idx, int width); @@ -149,6 +194,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> virtual FloatRegBits readFloatRegBits(int reg_idx); + /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); virtual void setFloatReg(int reg_idx, FloatReg val, int width); @@ -159,14 +205,18 @@ class AlphaFullCPU : public FullO3CPU<Impl> virtual void setFloatRegBits(int reg_idx, FloatRegBits val); + /** Reads this thread's PC. */ virtual uint64_t readPC() { return cpu->readPC(thread->tid); } + /** Sets this thread's PC. */ virtual void setPC(uint64_t val); + /** Reads this thread's next PC. */ virtual uint64_t readNextPC() { return cpu->readNextPC(thread->tid); } + /** Sets this thread's next PC. */ virtual void setNextPC(uint64_t val); virtual uint64_t readNextNPC() @@ -178,43 +228,60 @@ class AlphaFullCPU : public FullO3CPU<Impl> virtual void setNextNPC(uint64_t val) { panic("Alpha has no NextNPC!"); } + /** Reads a miscellaneous register. */ virtual MiscReg readMiscReg(int misc_reg) { return cpu->readMiscReg(misc_reg, thread->tid); } + /** Reads a misc. register, including any side-effects the + * read might have as defined by the architecture. */ virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->tid); } + /** Sets a misc. register. */ virtual Fault setMiscReg(int misc_reg, const MiscReg &val); + /** Sets a misc. register, including any side-effects the + * write might have as defined by the architecture. */ virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. virtual unsigned readStCondFailures() { return thread->storeCondFailures; } + /** Sets the number of consecutive store conditional failures. */ virtual void setStCondFailures(unsigned sc_failures) { thread->storeCondFailures = sc_failures; } #if FULL_SYSTEM + /** Returns if the thread is currently in PAL mode, based on + * the PC's value. */ virtual bool inPalMode() { return TheISA::PcPAL(cpu->readPC(thread->tid)); } #endif - // Only really makes sense for old CPU model. Lots of code // outside the CPU still checks this function, so it will // always return false to keep everything working. + /** Checks if the thread is misspeculating. Because it is + * very difficult to determine if the thread is + * misspeculating, this is set as false. */ virtual bool misspeculating() { return false; } #if !FULL_SYSTEM + /** Gets a syscall argument by index. */ virtual IntReg getSyscallArg(int i); + /** Sets a syscall argument. */ virtual void setSyscallArg(int i, IntReg val); + /** Sets the syscall return value. */ virtual void setSyscallReturn(SyscallReturn return_value); + /** Executes a syscall in SE mode. */ virtual void syscall(int64_t callnum) { return cpu->syscall(callnum, thread->tid); } + /** Reads the funcExeInst counter. */ virtual Counter readFuncExeInst() { return thread->funcExeInst; } #endif virtual void changeRegFileContext(TheISA::RegFile::ContextParam param, @@ -274,19 +341,32 @@ class AlphaFullCPU : public FullO3CPU<Impl> } #endif + /** Reads a miscellaneous register. */ MiscReg readMiscReg(int misc_reg, unsigned tid); + /** Reads a misc. register, including any side effects the read + * might have as defined by the architecture. + */ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid); + /** Sets a miscellaneous register. */ Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); + /** Sets a misc. register, including any side effects the write + * might have as defined by the architecture. + */ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); + /** Initiates a squash of all in-flight instructions for a given + * thread. The source of the squash is an external update of + * state through the XC. + */ void squashFromXC(unsigned tid); #if FULL_SYSTEM + /** Posts an interrupt. */ void post_interrupt(int int_num, int index); - + /** Reads the interrupt flag. */ int readIntrFlag(); /** Sets the interrupt flags. */ void setIntrFlag(int val); @@ -312,7 +392,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Executes a syscall. * @todo: Determine if this needs to be virtual. */ - void syscall(int64_t callnum, int thread_num); + void syscall(int64_t callnum, int tid); /** Gets a syscall argument. */ IntReg getSyscallArg(int i, int tid); @@ -438,6 +518,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> Addr lockAddr; + /** Temporary fix for the lock flag, works in the UP case. */ bool lockFlag; }; |