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Diffstat (limited to 'src/cpu/o3/comm.hh')
| -rw-r--r-- | src/cpu/o3/comm.hh | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh index a425484f5..4da251104 100644 --- a/src/cpu/o3/comm.hh +++ b/src/cpu/o3/comm.hh @@ -185,8 +185,9 @@ struct TimeBufStruct { /// Instruction that caused the a non-mispredict squash DynInstPtr squashInst; // *F - /// Hack for now to send back an uncached access to the IEW stage. - DynInstPtr uncachedLoad; // *I + /// Hack for now to send back a strictly ordered access to the + /// IEW stage. + DynInstPtr strictlyOrderedLoad; // *I /// Communication specifically to the IQ to tell the IQ that it can /// schedule a non-speculative instruction. @@ -216,8 +217,9 @@ struct TimeBufStruct { /// If the interrupt ended up being cleared before being handled bool clearInterrupt; // *F - /// Hack for now to send back an uncached access to the IEW stage. - bool uncached; // *I + /// Hack for now to send back an strictly ordered access to + /// the IEW stage. + bool strictlyOrdered; // *I }; |