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Diffstat (limited to 'src/cpu/o3/commit.hh')
| -rw-r--r-- | src/cpu/o3/commit.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index c76d6c1d0..62aa274c2 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -479,6 +479,12 @@ class DefaultCommit /** True if last committed microop can be followed by an interrupt */ bool canHandleInterrupts; + /** Have we had an interrupt pending and then seen it de-asserted because + of a masking change? In this case the variable is set and the next time + interrupts are enabled and pending the pipeline will squash to avoid + a possible livelock senario. */ + bool avoidQuiesceLiveLock; + /** Updates commit stats based on this instruction. */ void updateComInstStats(DynInstPtr &inst); |