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-rw-r--r--src/cpu/o3/commit_impl.hh7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index d8236f077..c3c4983c5 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -988,20 +988,19 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
"instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
head_inst->seqNum, head_inst->readPC());
-#if !FULL_SYSTEM
// Hack to make sure syscalls/memory barriers/quiesces
// aren't executed until all stores write back their data.
// This direct communication shouldn't be used for
// anything other than this.
- if (inst_num > 0 || iewStage->hasStoresToWB())
-#else
if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
head_inst->isQuiesce()) &&
iewStage->hasStoresToWB())
-#endif
{
DPRINTF(Commit, "Waiting for all stores to writeback.\n");
return false;
+ } else if (inst_num > 0) {
+ DPRINTF(Commit, "Waiting to become head of commit.\n");
+ return false;
}
toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;