diff options
Diffstat (limited to 'src/cpu/o3/commit_impl.hh')
-rw-r--r-- | src/cpu/o3/commit_impl.hh | 78 |
1 files changed, 46 insertions, 32 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index ec3d61050..2aa9d7824 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -644,7 +644,7 @@ template <class Impl> void DefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst) { - DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", + DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%llu]\n", tid, head_inst->seqNum); assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst); @@ -679,7 +679,7 @@ DefaultCommit<Impl>::tick() if (rob->isDoneSquashing(tid)) { commitStatus[tid] = Running; } else { - DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" + DPRINTF(Commit,"[tid:%i] Still Squashing, cannot commit any" " insts this cycle.\n", tid); rob->doSquash(tid); toIEW->commitInfo[tid].robSquashing = true; @@ -704,7 +704,7 @@ DefaultCommit<Impl>::tick() const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid); - DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" + DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of" " ROB and ready to commit\n", tid, inst->seqNum, inst->pcState()); @@ -713,12 +713,12 @@ DefaultCommit<Impl>::tick() ppCommitStall->notify(inst); - DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " + DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%llu] PC " "%s is head of ROB and not ready\n", tid, inst->seqNum, inst->pcState()); } - DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", + DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n", tid, rob->countInsts(tid), rob->numFreeEntries(tid)); } @@ -862,17 +862,18 @@ DefaultCommit<Impl>::commit() if (fromIEW->mispredictInst[tid]) { DPRINTF(Commit, - "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", + "[tid:%i] Squashing due to branch mispred " + "PC:%#x [sn:%llu]\n", tid, fromIEW->mispredictInst[tid]->instAddr(), fromIEW->squashedSeqNum[tid]); } else { DPRINTF(Commit, - "[tid:%i]: Squashing due to order violation [sn:%i]\n", + "[tid:%i] Squashing due to order violation [sn:%llu]\n", tid, fromIEW->squashedSeqNum[tid]); } - DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", + DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n", tid, fromIEW->pc[tid].nextInstAddr()); @@ -1010,8 +1011,9 @@ DefaultCommit<Impl>::commitInsts() assert(tid == commit_thread); - DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", - head_inst->seqNum, tid); + DPRINTF(Commit, + "Trying to commit head instruction, [tid:%i] [sn:%llu]\n", + tid, head_inst->seqNum); // If the head instruction is squashed, it is ready to retire // (be removed from the ROB) at any time. @@ -1132,7 +1134,7 @@ DefaultCommit<Impl>::commitInsts() squashAfter(tid, head_inst); } else { DPRINTF(Commit, "Unable to commit head instruction PC:%s " - "[tid:%i] [sn:%i].\n", + "[tid:%i] [sn:%llu].\n", head_inst->pcState(), tid ,head_inst->seqNum); break; } @@ -1169,12 +1171,17 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) || head_inst->isAtomic() || (head_inst->isLoad() && head_inst->strictlyOrdered())); - DPRINTF(Commit, "Encountered a barrier or non-speculative " - "instruction [sn:%lli] at the head of the ROB, PC %s.\n", - head_inst->seqNum, head_inst->pcState()); + DPRINTF(Commit, + "Encountered a barrier or non-speculative " + "instruction [tid:%i] [sn:%llu] " + "at the head of the ROB, PC %s.\n", + tid, head_inst->seqNum, head_inst->pcState()); if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { - DPRINTF(Commit, "Waiting for all stores to writeback.\n"); + DPRINTF(Commit, + "[tid:%i] [sn:%llu] " + "Waiting for all stores to writeback.\n", + tid, head_inst->seqNum); return false; } @@ -1185,8 +1192,9 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) head_inst->clearCanCommit(); if (head_inst->isLoad() && head_inst->strictlyOrdered()) { - DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n", - head_inst->seqNum, head_inst->pcState()); + DPRINTF(Commit, "[tid:%i] [sn:%llu] " + "Strictly ordered load, PC %s.\n", + tid, head_inst->seqNum, head_inst->pcState()); toIEW->commitInfo[tid].strictlyOrdered = true; toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst; } else { @@ -1210,11 +1218,14 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) } if (inst_fault != NoFault) { - DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", - head_inst->seqNum, head_inst->pcState()); + DPRINTF(Commit, "Inst [tid:%i] [sn:%llu] PC %s has a fault\n", + tid, head_inst->seqNum, head_inst->pcState()); if (iewStage->hasStoresToWB(tid) || inst_num > 0) { - DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); + DPRINTF(Commit, + "[tid:%i] [sn:%llu] " + "Stores outstanding, fault must wait.\n", + tid, head_inst->seqNum); return false; } @@ -1249,8 +1260,9 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) commitStatus[tid] = TrapPending; - DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", - head_inst->seqNum); + DPRINTF(Commit, + "[tid:%i] [sn:%llu] Committing instruction with fault\n", + tid, head_inst->seqNum); if (head_inst->traceData) { if (DTRACE(ExecFaulting)) { head_inst->traceData->setFetchSeq(head_inst->seqNum); @@ -1284,8 +1296,9 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) } } } - DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", - head_inst->seqNum, head_inst->pcState()); + DPRINTF(Commit, + "[tid:%i] [sn:%llu] Committing instruction with PC %s\n", + tid, head_inst->seqNum, head_inst->pcState()); if (head_inst->traceData) { head_inst->traceData->setFetchSeq(head_inst->seqNum); head_inst->traceData->setCPSeq(thread[tid]->numOp); @@ -1294,8 +1307,9 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num) head_inst->traceData = NULL; } if (head_inst->isReturn()) { - DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n", - head_inst->seqNum, head_inst->pcState()); + DPRINTF(Commit, + "[tid:%i] [sn:%llu] Return Instruction Committed PC %s \n", + tid, head_inst->seqNum, head_inst->pcState()); } // Update the commit rename map @@ -1339,8 +1353,8 @@ DefaultCommit<Impl>::getInsts() commitStatus[tid] != TrapPending) { changedROBNumEntries[tid] = true; - DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", - inst->pcState(), inst->seqNum, tid); + DPRINTF(Commit, "[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n", + inst->seqNum, tid, inst->pcState()); rob->insertInst(inst); @@ -1348,9 +1362,9 @@ DefaultCommit<Impl>::getInsts() youngestSeqNum[tid] = inst->seqNum; } else { - DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " - "squashed, skipping.\n", - inst->pcState(), inst->seqNum, tid); + DPRINTF(Commit, "[tid:%i] [sn:%llu] " + "Instruction PC %s was squashed, skipping.\n", + inst->seqNum, tid, inst->pcState()); } } } @@ -1364,7 +1378,7 @@ DefaultCommit<Impl>::markCompletedInsts() for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) { assert(fromIEW->insts[inst_num]); if (!fromIEW->insts[inst_num]->isSquashed()) { - DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " + DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%llu] ready " "within ROB.\n", fromIEW->insts[inst_num]->threadNumber, fromIEW->insts[inst_num]->pcState(), |