diff options
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r-- | src/cpu/o3/cpu.cc | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 393b9a189..53250d495 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -646,12 +646,6 @@ FullO3CPU<Impl>::init() { BaseCPU::init(); - if (!params()->switched_out && - system->getMemoryMode() != Enums::timing) { - fatal("The O3 CPU requires the memory system to be in " - "'timing' mode.\n"); - } - for (ThreadID tid = 0; tid < numThreads; ++tid) { // Set noSquashFromTC so that the CPU doesn't squash when initially // setting up registers. @@ -1262,11 +1256,7 @@ FullO3CPU<Impl>::drainResume() return; DPRINTF(Drain, "Resuming...\n"); - - if (system->getMemoryMode() != Enums::timing) { - fatal("The O3 CPU requires the memory system to be in " - "'timing' mode.\n"); - } + verifyMemoryMode(); fetch.drainResume(); commit.drainResume(); @@ -1323,6 +1313,16 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) } template <class Impl> +void +FullO3CPU<Impl>::verifyMemoryMode() const +{ + if (system->getMemoryMode() != Enums::timing) { + fatal("The O3 CPU requires the memory system to be in " + "'timing' mode.\n"); + } +} + +template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) { |