diff options
Diffstat (limited to 'src/cpu/o3/cpu.cc')
| -rw-r--r-- | src/cpu/o3/cpu.cc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 8f399e9f5..c65e509f9 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1244,14 +1244,14 @@ FullO3CPU<Impl>::verifyMemoryMode() const } template <class Impl> -TheISA::MiscReg +RegVal FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const { return this->isa[tid]->readMiscRegNoEffect(misc_reg); } template <class Impl> -TheISA::MiscReg +RegVal FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) { miscRegfileReads++; @@ -1261,7 +1261,7 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) template <class Impl> void FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, - const TheISA::MiscReg &val, ThreadID tid) + const RegVal &val, ThreadID tid) { this->isa[tid]->setMiscRegNoEffect(misc_reg, val); } @@ -1269,14 +1269,14 @@ FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, template <class Impl> void FullO3CPU<Impl>::setMiscReg(int misc_reg, - const TheISA::MiscReg &val, ThreadID tid) + const RegVal &val, ThreadID tid) { miscRegfileWrites++; this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); } template <class Impl> -uint64_t +RegVal FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) { intRegfileReads++; @@ -1284,7 +1284,7 @@ FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) } template <class Impl> -FloatRegBits +RegVal FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) { fpRegfileReads++; @@ -1327,7 +1327,7 @@ FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) template <class Impl> void -FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) +FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) { intRegfileWrites++; regFile.setIntReg(phys_reg, val); @@ -1335,7 +1335,7 @@ FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) template <class Impl> void -FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) +FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) { fpRegfileWrites++; regFile.setFloatRegBits(phys_reg, val); @@ -1366,7 +1366,7 @@ FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val) } template <class Impl> -uint64_t +RegVal FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) { intRegfileReads++; @@ -1377,7 +1377,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) } template <class Impl> -uint64_t +RegVal FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid) { fpRegfileReads++; @@ -1430,7 +1430,7 @@ FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) +FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) { intRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( @@ -1441,7 +1441,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid) +FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid) { fpRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( |