diff options
Diffstat (limited to 'src/cpu/o3/cpu.hh')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index b5f754056..30ed4ef3b 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -107,6 +107,8 @@ class FullO3CPU : public BaseO3CPU using VecElem = TheISA::VecElem; using VecRegContainer = TheISA::VecRegContainer; + using VecPredRegContainer = TheISA::VecPredRegContainer; + typedef O3ThreadState<Impl> ImplState; typedef O3ThreadState<Impl> Thread; @@ -457,6 +459,10 @@ class FullO3CPU : public BaseO3CPU const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; + const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; + + VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); + TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); void setIntReg(PhysRegIdPtr phys_reg, RegVal val); @@ -467,6 +473,8 @@ class FullO3CPU : public BaseO3CPU void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); + void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); + void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); RegVal readArchIntReg(int reg_idx, ThreadID tid); @@ -501,6 +509,11 @@ class FullO3CPU : public BaseO3CPU const VecElem& readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, ThreadID tid) const; + const VecPredRegContainer& readArchVecPredReg(int reg_idx, + ThreadID tid) const; + + VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); + TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); /** Architectural register accessors. Looks up in the commit @@ -512,6 +525,9 @@ class FullO3CPU : public BaseO3CPU void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); + void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, + ThreadID tid); + void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, @@ -805,6 +821,9 @@ class FullO3CPU : public BaseO3CPU //number of vector register file accesses mutable Stats::Scalar vecRegfileReads; Stats::Scalar vecRegfileWrites; + //number of predicate register file accesses + mutable Stats::Scalar vecPredRegfileReads; + Stats::Scalar vecPredRegfileWrites; //number of CC register file accesses Stats::Scalar ccRegfileReads; Stats::Scalar ccRegfileWrites; |