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-rw-r--r--src/cpu/o3/cpu.hh12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index f16450d19..aa02ee2ea 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -427,8 +427,6 @@ class FullO3CPU : public BaseO3CPU
TheISA::CCReg readCCReg(int reg_idx);
- const TheISA::VectorReg &readVectorReg(int reg_idx);
-
void setIntReg(int reg_idx, uint64_t val);
void setFloatReg(int reg_idx, TheISA::FloatReg val);
@@ -437,8 +435,6 @@ class FullO3CPU : public BaseO3CPU
void setCCReg(int reg_idx, TheISA::CCReg val);
- void setVectorReg(int reg_idx, const TheISA::VectorReg &val);
-
uint64_t readArchIntReg(int reg_idx, ThreadID tid);
float readArchFloatReg(int reg_idx, ThreadID tid);
@@ -447,8 +443,6 @@ class FullO3CPU : public BaseO3CPU
TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
- const TheISA::VectorReg &readArchVectorReg(int reg_idx, ThreadID tid);
-
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
* architected register first, then accesses that physical
@@ -462,9 +456,6 @@ class FullO3CPU : public BaseO3CPU
void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
- void setArchVectorReg(int reg_idx, const TheISA::VectorReg &val,
- ThreadID tid);
-
/** Sets the commit PC state of a specific thread. */
void pcState(const TheISA::PCState &newPCState, ThreadID tid);
@@ -743,9 +734,6 @@ class FullO3CPU : public BaseO3CPU
//number of CC register file accesses
Stats::Scalar ccRegfileReads;
Stats::Scalar ccRegfileWrites;
- //number of integer register file accesses
- Stats::Scalar vectorRegfileReads;
- Stats::Scalar vectorRegfileWrites;
//number of misc
Stats::Scalar miscRegfileReads;
Stats::Scalar miscRegfileWrites;