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-rw-r--r--src/cpu/o3/cpu.hh22
1 files changed, 19 insertions, 3 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 84a7c8673..d97a2080d 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -94,9 +94,9 @@ class FullO3CPU : public BaseO3CPU
public:
// Typedefs from the Impl here.
typedef typename Impl::CPUPol CPUPolicy;
- typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::O3CPU O3CPU;
+ typedef typename Impl::Params Params;
typedef O3ThreadState<Impl> Thread;
@@ -113,10 +113,8 @@ class FullO3CPU : public BaseO3CPU
SwitchedOut
};
-#if FULL_SYSTEM
TheISA::ITB * itb;
TheISA::DTB * dtb;
-#endif
/** Overall CPU status. */
Status _status;
@@ -265,6 +263,24 @@ class FullO3CPU : public BaseO3CPU
/** Registers statistics. */
void fullCPURegStats();
+ /** Translates instruction requestion. */
+ Fault translateInstReq(RequestPtr &req, Thread *thread)
+ {
+ return this->itb->translate(req, thread->getTC());
+ }
+
+ /** Translates data read request. */
+ Fault translateDataReadReq(RequestPtr &req, Thread *thread)
+ {
+ return this->dtb->translate(req, thread->getTC(), false);
+ }
+
+ /** Translates data write request. */
+ Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
+ {
+ return this->dtb->translate(req, thread->getTC(), true);
+ }
+
/** Returns a specific port. */
Port *getPort(const std::string &if_name, int idx);