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-rw-r--r--src/cpu/o3/decode_impl.hh4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index c9d0a1885..ce6738456 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -273,6 +273,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
///explicitly for ISAs with delay slots.
toFetch->decodeInfo[tid].nextNPC =
inst->branchTarget() + sizeof(TheISA::MachInst);
+ toFetch->decodeInfo[tid].nextMicroPC = inst->readMicroPC();
#if ISA_HAS_DELAY_SLOT
toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
@@ -735,7 +736,8 @@ DefaultDecode<Impl>::decodeInsts(unsigned tid)
// a check at the end
squash(inst, inst->threadNumber);
Addr target = inst->branchTarget();
- inst->setPredTarg(target, target + sizeof(TheISA::MachInst));
+ //The micro pc after an instruction level branch should be 0
+ inst->setPredTarg(target, target + sizeof(TheISA::MachInst), 0);
break;
}
}