summaryrefslogtreecommitdiff
path: root/src/cpu/o3/dyn_inst.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/o3/dyn_inst.hh')
-rw-r--r--src/cpu/o3/dyn_inst.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 9054b2089..5bd0f8e47 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -146,7 +146,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
* might have as defined by the architecture.
*/
void
- setMiscReg(int misc_reg, const RegVal &val)
+ setMiscReg(int misc_reg, RegVal val)
{
/** Writes to misc. registers are recorded and deferred until the
* commit stage, when updateMiscRegs() is called. First, check if
@@ -182,7 +182,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
* might have as defined by the architecture.
*/
void
- setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
+ setMiscRegOperand(const StaticInst *si, int idx, RegVal val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());