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Diffstat (limited to 'src/cpu/o3/dyn_inst_decl.hh')
-rw-r--r-- | src/cpu/o3/dyn_inst_decl.hh | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/cpu/o3/dyn_inst_decl.hh b/src/cpu/o3/dyn_inst_decl.hh new file mode 100644 index 000000000..750c3279d --- /dev/null +++ b/src/cpu/o3/dyn_inst_decl.hh @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + */ + +#ifndef __CPU_O3_DYN_INST_DECL_HH__ +#define __CPU_O3_DYN_INST_DECL_HH__ + +#include "arch/isa_specific.hh" + +template <class Impl> class BaseO3DynInst; +#if THE_ISA == ALPHA_ISA + struct AlphaSimpleImpl; + typedef BaseO3DynInst<AlphaSimpleImpl> O3DynInst; +#elif THE_ISA == MIPS_ISA + struct MipsSimpleImpl; + typedef BaseO3DynInst<MipsSimpleImpl> O3DynInst; +#elif THE_ISA == SPARC_ISA + struct SparcSimpleImpl; + typedef BaseO3DynInst<SparcSimpleImpl> O3DynInst; +#elif THE_ISA == X86_ISA + struct X86SimpleImpl; + typedef BaseO3DynInst<X86SimpleImpl> O3DynInst; +#elif THE_ISA == ARM_ISA + struct ArmSimpleImpl; + typedef BaseO3DynInst<ArmSimpleImpl> O3DynInst; +#else + #error "O3DynInst not defined for this ISA" +#endif + +#endif // __CPU_O3_DYN_INST_DECL_HH__ |