1 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 3cf0773fd..b8766ad77 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -59,6 +59,8 @@
 #include "sim/probe/probe.hh"
 
 struct DerivO3CPUParams;
+template <class Impl>
+class FullO3CPU;
 
 /**
  * DefaultFetch class handles both single threaded and SMT fetch. Its
@@ -85,6 +87,31 @@ class DefaultFetch
     /** Typedefs from ISA. */
     typedef TheISA::MachInst MachInst;
 
+    /**
+     * IcachePort class for instruction fetch.
+     */
+    class IcachePort : public MasterPort
+    {
+      protected:
+        /** Pointer to fetch. */
+        DefaultFetch<Impl> *fetch;
+
+      public:
+        /** Default constructor. */
+        IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
+            : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
+        { }
+
+      protected:
+
+        /** Timing version of receive.  Handles setting fetch to the
+         * proper status to start fetching. */
+        virtual bool recvTimingResp(PacketPtr pkt);
+
+        /** Handles doing a retry of a failed fetch. */
+        virtual void recvReqRetry();
+    };
+
     class FetchTranslation : public BaseTLB::Translation
     {
       protected:
@@ -353,6 +380,8 @@ class DefaultFetch
     /** The decoder. */
     TheISA::Decoder *decoder[Impl::MaxThreads];
 
+    MasterPort &getInstPort() { return icachePort; }
+
   private:
     DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
                          StaticInstPtr curMacroop, TheISA::PCState thisPC,
@@ -511,6 +540,9 @@ class DefaultFetch
      */
     bool interruptPending;
 
+    /** Instruction port. Note that it has to appear after the fetch stage. */
+    IcachePort icachePort;
+
     /** Set to true if a pipelined I-cache request should be issued. */
     bool issuePipelinedIfetch[Impl::MaxThreads];