summaryrefslogtreecommitdiff
path: root/src/cpu/o3/fetch_impl.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r--src/cpu/o3/fetch_impl.hh10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 880158dfc..736a66c64 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -902,8 +902,14 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
fromCommit->commitInfo[tid].doneSeqNum,
tid);
- // Also check if there's a mispredict that happened.
- if (fromCommit->commitInfo[tid].branchMispredict) {
+ // If it was a branch mispredict on a control instruction, update the
+ // branch predictor with that instruction, otherwise just kill the
+ // invalid state we generated in after sequence number
+ assert(!fromCommit->commitInfo[tid].branchMispredict ||
+ fromCommit->commitInfo[tid].mispredictInst);
+
+ if (fromCommit->commitInfo[tid].branchMispredict &&
+ fromCommit->commitInfo[tid].mispredictInst->isControl()) {
branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
fromCommit->commitInfo[tid].pc,
fromCommit->commitInfo[tid].branchTaken,