1 files changed, 11 insertions, 2 deletions

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 6b61b1b0e..23f101517 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -383,6 +383,7 @@ template <class Impl>
 void
 DefaultIEW<Impl>::switchOut()
 {
+    // IEW is ready to switch out at any time.
     cpu->signalSwitched();
 }
 
@@ -390,6 +391,7 @@ template <class Impl>
 void
 DefaultIEW<Impl>::doSwitchOut()
 {
+    // Clear any state.
     switchedOut = true;
 
     instQueue.switchOut();
@@ -408,6 +410,7 @@ template <class Impl>
 void
 DefaultIEW<Impl>::takeOverFrom()
 {
+    // Reset all state.
     _status = Active;
     exeStatus = Running;
     wbStatus = Idle;
@@ -521,6 +524,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
     toCommit->squashedSeqNum[tid] = inst->seqNum;
     toCommit->nextPC[tid] = inst->readPC();
 
+    // Must include the broadcasted SN in the squash.
     toCommit->includeSquashInst[tid] = true;
 
     ldstQueue.setLoadBlockedHandled(tid);
@@ -1054,6 +1058,7 @@ DefaultIEW<Impl>::dispatchInsts(unsigned tid)
                 // Store conditionals need to be set as "canCommit()"
                 // so that commit can process them when they reach the
                 // head of commit.
+                // @todo: This is somewhat specific to Alpha.
                 inst->setCanCommit();
                 instQueue.insertNonSpec(inst);
                 add_to_iq = false;
@@ -1313,6 +1318,7 @@ DefaultIEW<Impl>::executeInsts()
         }
     }
 
+    // Update and record activity if we processed any instructions.
     if (inst_num) {
         if (exeStatus == Idle) {
             exeStatus = Running;
@@ -1363,8 +1369,10 @@ DefaultIEW<Impl>::writebackInsts()
                 scoreboard->setReg(inst->renamedDestRegIdx(i));
             }
 
-            producerInst[tid]++;
-            consumerInst[tid]+= dependents;
+            if (dependents) {
+                producerInst[tid]++;
+                consumerInst[tid]+= dependents;
+            }
             writebackCount[tid]++;
         }
     }
@@ -1435,6 +1443,7 @@ DefaultIEW<Impl>::tick()
 
         DPRINTF(IEW,"Processing [tid:%i]\n",tid);
 
+        // Update structures based on instructions committed.
         if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
             !fromCommit->commitInfo[tid].squash &&
             !fromCommit->commitInfo[tid].robSquashing) {