1 files changed, 64 insertions, 5 deletions

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 684ae2295..c4ec93b3e 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -73,6 +73,7 @@ DefaultIEW<Impl>::DefaultIEW(Params *params)
         dispatchStatus[i] = Running;
         stalls[i].commit = false;
         fetchRedirect[i] = false;
+        bdelayDoneSeqNum[i] = 0;
     }
 
     wbMax = wbWidth * params->wbDepth;
@@ -428,13 +429,31 @@ DefaultIEW<Impl>::squash(unsigned tid)
     instQueue.squash(tid);
 
     // Tell the LDSTQ to start squashing.
+#if THE_ISA == ALPHA_ISA
     ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
-
+#else
+    ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
+#endif
     updatedQueues = true;
 
     // Clear the skid buffer in case it has any data in it.
-    while (!skidBuffer[tid].empty()) {
+    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
+            tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
 
+    while (!skidBuffer[tid].empty()) {
+#if THE_ISA != ALPHA_ISA
+        if (skidBuffer[tid].front()->seqNum <=
+            fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
+            DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
+                    "that occur before delay slot [sn:%i].\n",
+                    fromCommit->commitInfo[tid].bdelayDoneSeqNum,
+                    tid);
+            break;
+        } else {
+            DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
+                    "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
+        }
+#endif
         if (skidBuffer[tid].front()->isLoad() ||
             skidBuffer[tid].front()->isStore() ) {
             toRename->iewInfo[tid].dispatchedToLSQ++;
@@ -445,6 +464,8 @@ DefaultIEW<Impl>::squash(unsigned tid)
         skidBuffer[tid].pop();
     }
 
+    bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+
     emptyRenameInsts(tid);
 }
 
@@ -458,10 +479,26 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
     toCommit->squash[tid] = true;
     toCommit->squashedSeqNum[tid] = inst->seqNum;
     toCommit->mispredPC[tid] = inst->readPC();
-    toCommit->nextPC[tid] = inst->readNextPC();
     toCommit->branchMispredict[tid] = true;
+
+#if THE_ISA == ALPHA_ISA
     toCommit->branchTaken[tid] = inst->readNextPC() !=
         (inst->readPC() + sizeof(TheISA::MachInst));
+    toCommit->nextPC[tid] = inst->readNextPC();
+#else
+    bool branch_taken = inst->readNextNPC() !=
+        (inst->readNextPC() + sizeof(TheISA::MachInst));
+
+    toCommit->branchTaken[tid] = branch_taken;
+
+    toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
+
+    if (inst->isCondDelaySlot() && branch_taken) {
+        toCommit->nextPC[tid] = inst->readNextPC();
+    } else {
+        toCommit->nextPC[tid] = inst->readNextNPC();
+    }
+#endif
 
     toCommit->includeSquashInst[tid] = false;
 
@@ -825,9 +862,11 @@ DefaultIEW<Impl>::sortInsts()
 {
     int insts_from_rename = fromRename->size;
 #ifdef DEBUG
+#if THE_ISA == ALPHA_ISA
     for (int i = 0; i < numThreads; i++)
         assert(insts[i].empty());
 #endif
+#endif
     for (int i = 0; i < insts_from_rename; ++i) {
         insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
     }
@@ -837,7 +876,23 @@ template <class Impl>
 void
 DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
 {
+    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
+            "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
+
     while (!insts[tid].empty()) {
+
+#if THE_ISA != ALPHA_ISA
+        if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
+            DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
+                    " that occurs at or before delay slot [sn:%i].\n",
+                    tid, bdelayDoneSeqNum[tid]);
+            break;
+        } else {
+            DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
+                    "[sn:%i].\n", tid, insts[tid].front()->seqNum);
+        }
+#endif
+
         if (insts[tid].front()->isLoad() ||
             insts[tid].front()->isStore() ) {
             toRename->iewInfo[tid].dispatchedToLSQ++;
@@ -1120,7 +1175,7 @@ DefaultIEW<Impl>::dispatchInsts(unsigned tid)
     }
 
     if (!insts_to_dispatch.empty()) {
-        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
+        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
         block(tid);
         toRename->iewUnblock[tid] = false;
     }
@@ -1263,9 +1318,13 @@ DefaultIEW<Impl>::executeInsts()
                 fetchRedirect[tid] = true;
 
                 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
+#if THE_ISA == ALPHA_ISA
                 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
                         inst->nextPC);
-
+#else
+                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
+                        inst->nextNPC);
+#endif
                 // If incorrect, then signal the ROB that it must be squashed.
                 squashDueToBranch(inst, tid);