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Diffstat (limited to 'src/cpu/o3/iew_impl.hh')
-rw-r--r--src/cpu/o3/iew_impl.hh92
1 files changed, 53 insertions, 39 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 6434ec8c3..56c182564 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -462,7 +462,7 @@ template<class Impl>
void
DefaultIEW<Impl>::squash(ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
+ DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid);
// Tell the IQ to start squashing.
instQueue.squash(tid);
@@ -472,8 +472,10 @@ DefaultIEW<Impl>::squash(ThreadID tid)
updatedQueues = true;
// Clear the skid buffer in case it has any data in it.
- DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
- tid, fromCommit->commitInfo[tid].doneSeqNum);
+ DPRINTF(IEW,
+ "Removing skidbuffer instructions until "
+ "[sn:%llu] [tid:%i]\n",
+ fromCommit->commitInfo[tid].doneSeqNum, tid);
while (!skidBuffer[tid].empty()) {
if (skidBuffer[tid].front()->isLoad()) {
@@ -496,8 +498,9 @@ template<class Impl>
void
DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
- "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
+ DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction,"
+ " PC: %s "
+ "\n", tid, inst->seqNum, inst->pcState() );
if (!toCommit->squash[tid] ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
@@ -521,8 +524,8 @@ template<class Impl>
void
DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
- "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
+ DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger "
+ "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
// Need to include inst->seqNum in the following comparison to cover the
// corner case when a branch misprediction and a memory violation for the
// same instruction (e.g. load PC) are detected in the same cycle. In this
@@ -548,7 +551,7 @@ template<class Impl>
void
DefaultIEW<Impl>::block(ThreadID tid)
{
- DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
+ DPRINTF(IEW, "[tid:%i] Blocking.\n", tid);
if (dispatchStatus[tid] != Blocked &&
dispatchStatus[tid] != Unblocking) {
@@ -567,7 +570,7 @@ template<class Impl>
void
DefaultIEW<Impl>::unblock(ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
+ DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid "
"buffer %u.\n",tid, tid);
// If the skid bufffer is empty, signal back to previous stages to unblock.
@@ -575,7 +578,7 @@ DefaultIEW<Impl>::unblock(ThreadID tid)
if (skidBuffer[tid].empty()) {
toRename->iewUnblock[tid] = true;
wroteToTimeBuffer = true;
- DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
+ DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid);
dispatchStatus[tid] = Running;
}
}
@@ -669,7 +672,7 @@ DefaultIEW<Impl>::skidInsert(ThreadID tid)
insts[tid].pop();
- DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
+ DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into "
"dispatch skidBuffer %i\n",tid, inst->seqNum,
inst->pcState(),tid);
@@ -764,10 +767,10 @@ DefaultIEW<Impl>::checkStall(ThreadID tid)
bool ret_val(false);
if (fromCommit->commitInfo[tid].robSquashing) {
- DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
+ DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid);
ret_val = true;
} else if (instQueue.isFull(tid)) {
- DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
+ DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid);
ret_val = true;
}
@@ -800,7 +803,7 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
}
if (fromCommit->commitInfo[tid].robSquashing) {
- DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
+ DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid);
dispatchStatus[tid] = Squashing;
emptyRenameInsts(tid);
@@ -816,7 +819,7 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
if (dispatchStatus[tid] == Blocked) {
// Status from previous cycle was blocked, but there are no more stall
// conditions. Switch over to unblocking.
- DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
+ DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n",
tid);
dispatchStatus[tid] = Unblocking;
@@ -829,7 +832,7 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
if (dispatchStatus[tid] == Squashing) {
// Switch status to running if rename isn't being told to block or
// squash this cycle.
- DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
+ DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n",
tid);
dispatchStatus[tid] = Running;
@@ -856,7 +859,7 @@ template <class Impl>
void
DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
+ DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid);
while (!insts[tid].empty()) {
@@ -978,14 +981,14 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
inst = insts_to_dispatch.front();
if (dispatchStatus[tid] == Unblocking) {
- DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
+ DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid "
"buffer\n", tid);
}
// Make sure there's a valid instruction there.
assert(inst);
- DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
+ DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to "
"IQ.\n",
tid, inst->pcState(), inst->seqNum, inst->threadNumber);
@@ -995,7 +998,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
// Check for squashed instructions.
if (inst->isSquashed()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
+ DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, "
"not adding to IQ.\n", tid);
++iewDispSquashedInsts;
@@ -1017,7 +1020,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
// Check for full conditions.
if (instQueue.isFull(tid)) {
- DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
+ DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid);
// Call function to start blocking.
block(tid);
@@ -1035,7 +1038,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
(inst->isLoad() && ldstQueue.lqFull(tid)) ||
(inst->isStore() && ldstQueue.sqFull(tid))) {
- DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
+ DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid,
inst->isLoad() ? "LQ" : "SQ");
// Call function to start blocking.
@@ -1052,7 +1055,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
// Otherwise issue the instruction just fine.
if (inst->isAtomic()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
"encountered, adding to LSQ.\n", tid);
ldstQueue.insertStore(inst);
@@ -1070,7 +1073,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
toRename->iewInfo[tid].dispatchedToSQ++;
} else if (inst->isLoad()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
"encountered, adding to LSQ.\n", tid);
// Reserve a spot in the load store queue for this
@@ -1083,7 +1086,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
toRename->iewInfo[tid].dispatchedToLQ++;
} else if (inst->isStore()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
"encountered, adding to LSQ.\n", tid);
ldstQueue.insertStore(inst);
@@ -1111,7 +1114,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
instQueue.insertBarrier(inst);
add_to_iq = false;
} else if (inst->isNop()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
+ DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, "
"skipping.\n", tid);
inst->setIssued();
@@ -1129,7 +1132,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
}
if (add_to_iq && inst->isNonSpeculative()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction "
"encountered, skipping.\n", tid);
// Same as non-speculative stores.
@@ -1162,7 +1165,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
}
if (!insts_to_dispatch.empty()) {
- DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
+ DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid);
block(tid);
toRename->iewUnblock[tid] = false;
}
@@ -1228,7 +1231,7 @@ DefaultIEW<Impl>::executeInsts()
DynInstPtr inst = instQueue.getInstToExecute();
- DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
+ DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n",
inst->pcState(), inst->threadNumber,inst->seqNum);
// Notify potential listeners that this instruction has started
@@ -1238,7 +1241,7 @@ DefaultIEW<Impl>::executeInsts()
// Check if the instruction is squashed; if so then skip it
if (inst->isSquashed()) {
DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
- " [sn:%i]\n", inst->pcState(), inst->threadNumber,
+ " [sn:%llu]\n", inst->pcState(), inst->threadNumber,
inst->seqNum);
// Consider this instruction executed so that commit can go
@@ -1366,11 +1369,15 @@ DefaultIEW<Impl>::executeInsts()
if (inst->mispredicted() && !loadNotExecuted) {
fetchRedirect[tid] = true;
- DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
- DPRINTF(IEW, "Predicted target was PC: %s.\n",
- inst->readPredTarg());
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
- inst->pcState());
+ DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
+ "Branch mispredict detected.\n",
+ tid,inst->seqNum);
+ DPRINTF(IEW, "[tid:%i] [sn:%llu] "
+ "Predicted target was PC: %s\n",
+ tid,inst->seqNum,inst->readPredTarg());
+ DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
+ "Redirecting fetch to PC: %s\n",
+ tid,inst->seqNum,inst->pcState());
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
@@ -1664,11 +1671,18 @@ DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst)
if (inst->mispredicted()) {
fetchRedirect[tid] = true;
- DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
- DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
+ DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
+ "Branch mispredict detected.\n",
+ tid,inst->seqNum);
+ DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target "
+ "was PC:%#x, NPC:%#x\n",
+ tid,inst->seqNum,
inst->predInstAddr(), inst->predNextInstAddr());
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
- " NPC: %#x.\n", inst->nextInstAddr(),
+ DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
+ "Redirecting fetch to PC: %#x, "
+ "NPC: %#x.\n",
+ tid,inst->seqNum,
+ inst->nextInstAddr(),
inst->nextInstAddr());
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 18:42:04 +0000