summaryrefslogtreecommitdiff
path: root/src/cpu/o3/inst_queue_impl.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/o3/inst_queue_impl.hh')
-rw-r--r--src/cpu/o3/inst_queue_impl.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 0a6d309fe..a30bf7f5f 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1182,8 +1182,12 @@ InstructionQueue<Impl>::getDeferredMemInstToExecute()
// 2. virtual fence ahead
// 3. not ready to expose and gets a TLB miss
// for both (2, 3) we need to restart the translation
+
+ DPRINTF(IQ, "sn:%lli onlyWaitForFence = %d, fenceDelay = %d\n", (*it)->seqNum, (*it)->onlyWaitForFence(), (*it)->fenceDelay() );
+
if ( (*it)->translationCompleted()
|| ((*it)->onlyWaitForFence() && !(*it)->fenceDelay())
+ || ((*it)->onlyWaitForExpose() && (*it)->readyToExpose())
|| (*it)->isSquashed()) {
DynInstPtr mem_inst = std::move(*it);
mem_inst->onlyWaitForFence(false);