diff options
Diffstat (limited to 'src/cpu/o3/inst_queue_impl.hh')
| -rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index aa12297d6..4a5262fd6 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -589,7 +589,7 @@ InstructionQueue<Impl>::insert(const DynInstPtr &new_inst) // Make sure the instruction is valid assert(new_inst); - DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", + DPRINTF(IQ, "Adding instruction [sn:%llu] PC %s to the IQ.\n", new_inst->seqNum, new_inst->pcState()); assert(freeEntries != 0); @@ -639,7 +639,7 @@ InstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) nonSpecInsts[new_inst->seqNum] = new_inst; - DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " + DPRINTF(IQ, "Adding non-speculative instruction [sn:%llu] PC %s " "to the IQ.\n", new_inst->seqNum, new_inst->pcState()); @@ -751,7 +751,7 @@ template <class Impl> void InstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) { - DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); + DPRINTF(IQ, "Processing FU completion [sn:%llu]\n", inst->seqNum); assert(!cpu->switchedOut()); // The CPU could have been sleeping until this op completed (*extremely* // long latency op). Wake it if it was. This may be overkill. @@ -886,7 +886,7 @@ InstructionQueue<Impl>::scheduleReadyInsts() } DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " - "[sn:%lli]\n", + "[sn:%llu]\n", tid, issuing_inst->pcState(), issuing_inst->seqNum); @@ -943,7 +943,7 @@ template <class Impl> void InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) { - DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " + DPRINTF(IQ, "Marking nonspeculative instruction [sn:%llu] as ready " "to execute.\n", inst); NonSpecMapIt inst_it = nonSpecInsts.find(inst); @@ -971,7 +971,7 @@ template <class Impl> void InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) { - DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", + DPRINTF(IQ, "[tid:%i] Committing instructions older than [sn:%llu]\n", tid,inst); ListIt iq_it = instList[tid].begin(); @@ -1042,7 +1042,7 @@ InstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); while (dep_inst) { - DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " + DPRINTF(IQ, "Waking up a dependent instruction, [sn:%llu] " "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); // Might want to give more information to the instruction @@ -1088,7 +1088,7 @@ InstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) } DPRINTF(IQ, "Instruction is ready to issue, putting it onto " - "the ready list, PC %s opclass:%i [sn:%lli].\n", + "the ready list, PC %s opclass:%i [sn:%llu].\n", ready_inst->pcState(), op_class, ready_inst->seqNum); } @@ -1096,7 +1096,7 @@ template <class Impl> void InstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) { - DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); + DPRINTF(IQ, "Rescheduling mem inst [sn:%llu]\n", resched_inst->seqNum); // Reset DTB translation state resched_inst->translationStarted(false); @@ -1119,7 +1119,7 @@ InstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) { ThreadID tid = completed_inst->threadNumber; - DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", + DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%llu]\n", completed_inst->pcState(), completed_inst->seqNum); ++freeEntries; @@ -1196,7 +1196,7 @@ template <class Impl> void InstructionQueue<Impl>::squash(ThreadID tid) { - DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " + DPRINTF(IQ, "[tid:%i] Starting to squash instructions in " "the IQ.\n", tid); // Read instruction sequence number of last instruction out of the @@ -1217,7 +1217,7 @@ InstructionQueue<Impl>::doSquash(ThreadID tid) ListIt squash_it = instList[tid].end(); --squash_it; - DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", + DPRINTF(IQ, "[tid:%i] Squashing until sequence number %i!\n", tid, squashedSeqNum[tid]); // Squash any instructions younger than the squashed sequence number @@ -1246,7 +1246,7 @@ InstructionQueue<Impl>::doSquash(ThreadID tid) (squashed_inst->isMemRef() && !squashed_inst->memOpDone())) { - DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", + DPRINTF(IQ, "[tid:%i] Instruction [sn:%llu] PC %s squashed.\n", tid, squashed_inst->seqNum, squashed_inst->pcState()); bool is_acq_rel = squashed_inst->isMemBarrier() && @@ -1460,7 +1460,7 @@ InstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) OpClass op_class = inst->opClass(); DPRINTF(IQ, "Instruction is ready to issue, putting it onto " - "the ready list, PC %s opclass:%i [sn:%lli].\n", + "the ready list, PC %s opclass:%i [sn:%llu].\n", inst->pcState(), op_class, inst->seqNum); readyInsts[op_class].push(inst); @@ -1531,7 +1531,7 @@ InstructionQueue<Impl>::dumpLists() cprintf("Non speculative list: "); while (non_spec_it != non_spec_end_it) { - cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), + cprintf("%s [sn:%llu]", (*non_spec_it).second->pcState(), (*non_spec_it).second->seqNum); ++non_spec_it; } @@ -1545,7 +1545,7 @@ InstructionQueue<Impl>::dumpLists() cprintf("List order: "); while (list_order_it != list_order_end_it) { - cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, + cprintf("%i OpClass:%i [sn:%llu] ", i, (*list_order_it).queueType, (*list_order_it).oldestInst); ++list_order_it; @@ -1580,7 +1580,7 @@ InstructionQueue<Impl>::dumpInsts() } } - cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" + cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n" "Issued:%i\nSquashed:%i\n", (*inst_list_it)->pcState(), (*inst_list_it)->seqNum, @@ -1622,7 +1622,7 @@ InstructionQueue<Impl>::dumpInsts() } } - cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" + cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n" "Issued:%i\nSquashed:%i\n", (*inst_list_it)->pcState(), (*inst_list_it)->seqNum, |