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-rw-r--r--src/cpu/o3/lsq.hh8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index e5c35a3a6..0e18aa145 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -136,14 +136,6 @@ class LSQ {
/** [mengjia]
- * Attempts to validate loads until all cache ports are used or the
- * interface becomes blocked.
- */
- int exposeLoads();
- /** Same as above, but only for one thread. */
- int exposeLoads(ThreadID tid);
-
- /** [mengjia]
* attempt to update FenceDelay state for load insts
*/
void updateVisibleState();