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Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index e9e3fea96..2bb42cadc 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -624,7 +624,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, // We'll say this has a 1 cycle load-store forwarding latency // for now. // @todo: Need to make this a parameter. - cpu->schedule(wb, curTick); + cpu->schedule(wb, curTick()); // Don't need to do anything special for split loads. if (TheISA::HasUnalignedMemAcc && sreqLow) { |