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-rw-r--r--src/cpu/o3/lsq_unit.hh3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index ad1e26d2f..c3bb8f7cd 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -41,7 +41,6 @@
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
-#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
@@ -271,7 +270,7 @@ class LSQUnit {
MasterPort *dcachePort;
/** Derived class to hold any sender state the LSQ needs. */
- class LSQSenderState : public Packet::SenderState, public FastAlloc
+ class LSQSenderState : public Packet::SenderState
{
public:
/** Default constructor. */