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Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 0882dcf20..3c1a4eda3 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -452,6 +452,9 @@ class LSQUnit { /** Has the blocked load been handled. */ bool loadBlockedHandled; + /** Whether or not a store is in flight. */ + bool storeInFlight; + /** The sequence number of the blocked load. */ InstSeqNum blockedLoadSeqNum; @@ -465,6 +468,9 @@ class LSQUnit { /** The packet that is pending free cache ports. */ PacketPtr pendingPkt; + /** Flag for memory model. */ + bool needsTSO; + // Will also need how many read/write ports the Dcache has. Or keep track // of that in stage that is one level up, and only call executeLoad/Store // the appropriate number of times. |