diff options
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 693bee82c..af926759c 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -115,12 +115,20 @@ class LSQUnit { /** Inserts a store instruction. */ void insertStore(DynInstPtr &store_inst); - /** Check for ordering violations in the LSQ + /** Check for ordering violations in the LSQ. For a store squash if we + * ever find a conflicting load. For a load, only squash if we + * an external snoop invalidate has been seen for that load address * @param load_idx index to start checking at * @param inst the instruction to check */ Fault checkViolations(int load_idx, DynInstPtr &inst); + /** Check if an incoming invalidate hits in the lsq on a load + * that might have issued out of order wrt another load beacuse + * of the intermediate invalidate. + */ + void checkSnoop(PacketPtr pkt); + /** Executes a load instruction. */ Fault executeLoad(DynInstPtr &inst); @@ -417,6 +425,9 @@ class LSQUnit { //list<InstSeqNum> mshrSeqNums; + /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */ + Addr cacheBlockMask; + /** Wire to read information from the issue stage time queue. */ typename TimeBuffer<IssueStruct>::wire fromIssue; |