1 files changed, 15 insertions, 13 deletions

diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index ffe66be6b..24f5c20ee 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -85,6 +85,7 @@ class MemDepUnit
 
   public:
     typedef typename Impl::DynInstPtr DynInstPtr;
+    typedef typename Impl::DynInstConstPtr DynInstConstPtr;
 
     /** Empty constructor. Must call init() prior to using in this case. */
     MemDepUnit();
@@ -117,22 +118,22 @@ class MemDepUnit
     void setIQ(InstructionQueue<Impl> *iq_ptr);
 
     /** Inserts a memory instruction. */
-    void insert(DynInstPtr &inst);
+    void insert(const DynInstPtr &inst);
 
     /** Inserts a non-speculative memory instruction. */
-    void insertNonSpec(DynInstPtr &inst);
+    void insertNonSpec(const DynInstPtr &inst);
 
     /** Inserts a barrier instruction. */
-    void insertBarrier(DynInstPtr &barr_inst);
+    void insertBarrier(const DynInstPtr &barr_inst);
 
     /** Indicate that an instruction has its registers ready. */
-    void regsReady(DynInstPtr &inst);
+    void regsReady(const DynInstPtr &inst);
 
     /** Indicate that a non-speculative instruction is ready. */
-    void nonSpecInstReady(DynInstPtr &inst);
+    void nonSpecInstReady(const DynInstPtr &inst);
 
     /** Reschedules an instruction to be re-executed. */
-    void reschedule(DynInstPtr &inst);
+    void reschedule(const DynInstPtr &inst);
 
     /** Replays all instructions that have been rescheduled by moving them to
      *  the ready list.
@@ -140,13 +141,13 @@ class MemDepUnit
     void replay();
 
     /** Completes a memory instruction. */
-    void completed(DynInstPtr &inst);
+    void completed(const DynInstPtr &inst);
 
     /** Completes a barrier instruction. */
-    void completeBarrier(DynInstPtr &inst);
+    void completeBarrier(const DynInstPtr &inst);
 
     /** Wakes any dependents of a memory instruction. */
-    void wakeDependents(DynInstPtr &inst);
+    void wakeDependents(const DynInstPtr &inst);
 
     /** Squashes all instructions up until a given sequence number for a
      *  specific thread.
@@ -154,10 +155,11 @@ class MemDepUnit
     void squash(const InstSeqNum &squashed_num, ThreadID tid);
 
     /** Indicates an ordering violation between a store and a younger load. */
-    void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
+    void violation(const DynInstPtr &store_inst,
+                   const DynInstPtr &violating_load);
 
     /** Issues the given instruction */
-    void issue(DynInstPtr &inst);
+    void issue(const DynInstPtr &inst);
 
     /** Debugging function to dump the lists of instructions. */
     void dumpLists();
@@ -176,7 +178,7 @@ class MemDepUnit
     class MemDepEntry {
       public:
         /** Constructs a memory dependence entry. */
-        MemDepEntry(DynInstPtr &new_inst)
+        MemDepEntry(const DynInstPtr &new_inst)
             : inst(new_inst), regsReady(false), memDepReady(false),
               completed(false), squashed(false)
         {
@@ -232,7 +234,7 @@ class MemDepUnit
     };
 
     /** Finds the memory dependence entry in the hash map. */
-    inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
+    inline MemDepEntryPtr &findInHash(const DynInstConstPtr& inst);
 
     /** Moves an entry to the ready list. */
     inline void moveToReady(MemDepEntryPtr &ready_inst_entry);