diff options
Diffstat (limited to 'src/cpu/o3/mips')
| -rwxr-xr-x | src/cpu/o3/mips/cpu.hh | 7 | ||||
| -rw-r--r-- | src/cpu/o3/mips/cpu_builder.cc | 6 | ||||
| -rw-r--r-- | src/cpu/o3/mips/cpu_impl.hh | 31 | ||||
| -rwxr-xr-x | src/cpu/o3/mips/dyn_inst.hh | 11 |
4 files changed, 16 insertions, 39 deletions
diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh index bf04b9f69..7e6268cdf 100755 --- a/src/cpu/o3/mips/cpu.hh +++ b/src/cpu/o3/mips/cpu.hh @@ -92,16 +92,15 @@ class MipsO3CPU : public FullO3CPU<Impl> /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg, - Fault &fault, unsigned tid); + TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, + void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc index f1c3b33a5..ee9f2b48d 100644 --- a/src/cpu/o3/mips/cpu_builder.cc +++ b/src/cpu/o3/mips/cpu_builder.cc @@ -54,8 +54,6 @@ Param<int> activity; SimObjectVectorParam<Process *> workload; -SimObjectParam<MemObject *> mem; - SimObjectParam<BaseCPU *> checker; Param<Counter> max_insts_any_thread; @@ -153,8 +151,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(workload, "Processes to run"), - INIT_PARAM(mem, "Memory"), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -284,8 +280,6 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; - params->mem = mem; - params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index e08741626..08e9ba483 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -58,24 +58,10 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params) if (i < params->workload.size()) { DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], - i, params->mem); + this->thread[i] = new Thread(this, i, params->workload[i], i); this->thread[i]->setStatus(ThreadContext::Suspended); - - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), i), - params->workload[i]->pTable, - false); - mem_port = params->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - this->thread[i]->setMemPort(trans_port); - //usedTids[i] = true; //threadMap[i] = i; } else { @@ -83,7 +69,7 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params) //when scheduling threads to CPU Process* dummy_proc = NULL; - this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem); + this->thread[i] = new Thread(this, i, dummy_proc, i); //usedTids[i] = false; } @@ -156,25 +142,24 @@ MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) template <class Impl> MiscReg -MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); + return this->regFile.readMiscRegWithEffect(misc_reg, tid); } template <class Impl> -Fault +void MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> -Fault +void MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template <class Impl> diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh index aa30bfa1e..9e95b2bfb 100755 --- a/src/cpu/o3/mips/dyn_inst.hh +++ b/src/cpu/o3/mips/dyn_inst.hh @@ -103,23 +103,22 @@ class MipsDynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, fault, - this->threadNumber); + return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { this->instResult.integer = val; - return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); + this->cpu->setMiscReg(misc_reg, val, this->threadNumber); } /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return this->cpu->setMiscRegWithEffect(misc_reg, val, this->threadNumber); |