diff options
Diffstat (limited to 'src/cpu/o3/rename_impl.hh')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 43b7ba9aa..b19b3414c 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -186,6 +186,15 @@ DefaultRename<Impl>::regStats() template <class Impl> void +DefaultRename<Impl>::regProbePoints() +{ + ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); + ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), + "SquashInRename"); +} + +template <class Impl> +void DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) { timeBuffer = tb_ptr; @@ -697,7 +706,9 @@ DefaultRename<Impl>::renameInsts(ThreadID tid) storesInProgress[tid]++; } ++renamed_insts; - + // Notify potential listeners that source and destination registers for + // this instruction have been renamed. + ppRename->notify(inst); // Put instruction in rename queue. toIEW->insts[toIEWIndex] = inst; @@ -929,6 +940,12 @@ DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) freeList->addReg(hb_it->newPhysReg); } + // Notify potential listeners that the register mapping needs to be + // removed because the instruction it was mapped to got squashed. Note + // that this is done before hb_it is incremented. + ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, + hb_it->newPhysReg)); + historyBuffer[tid].erase(hb_it++); ++renameUndoneMaps; |