diff options
Diffstat (limited to 'src/cpu/o3/rename_map.cc')
| -rw-r--r-- | src/cpu/o3/rename_map.cc | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index 27ddd8c63..b0232df20 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -99,9 +99,6 @@ UnifiedRenameMap::init(PhysRegFile *_regFile, floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); - - vectorMap.init(TheISA::NumVectorRegs, &(freeList->vectorList), - (RegIndex)-1); } @@ -120,9 +117,6 @@ UnifiedRenameMap::rename(RegIndex arch_reg) case CCRegClass: return renameCC(rel_arch_reg); - case VectorRegClass: - return renameVector(rel_arch_reg); - case MiscRegClass: return renameMisc(rel_arch_reg); @@ -148,9 +142,6 @@ UnifiedRenameMap::lookup(RegIndex arch_reg) const case CCRegClass: return lookupCC(rel_arch_reg); - case VectorRegClass: - return lookupVector(rel_arch_reg); - case MiscRegClass: return lookupMisc(rel_arch_reg); @@ -175,9 +166,6 @@ UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg) case CCRegClass: return setCCEntry(rel_arch_reg, phys_reg); - case VectorRegClass: - return setVectorEntry(rel_arch_reg, phys_reg); - case MiscRegClass: // Misc registers do not actually rename, so don't change // their mappings. We end up here when a commit or squash |