1 files changed, 13 insertions, 28 deletions

diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index 536a620bf..4a194cbda 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -55,12 +55,7 @@
 #endif
 
 template <class Impl>
-SparcO3CPU<Impl>::SparcO3CPU(Params *params)
-#if FULL_SYSTEM
-    : FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
-#else
-    : FullO3CPU<Impl>(params)
-#endif
+SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(params)
 {
     DPRINTF(O3CPU, "Creating SparcO3CPU object.\n");
 
@@ -172,15 +167,16 @@ SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
+SparcO3CPU<Impl>::setMiscReg(int misc_reg,
+        const SparcISA::MiscReg &val, unsigned tid)
 {
     this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
-                                       unsigned tid)
+SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
+        const SparcISA::MiscReg &val, unsigned tid)
 {
     this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
 }
@@ -285,35 +281,24 @@ template <class Impl>
 TheISA::IntReg
 SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
 {
-    return this->readArchIntReg(SparcISA::ArgumentReg0 + i, tid);
+    TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
+            SparcISA::ArgumentReg0 + i);
+    return this->readArchIntReg(idx, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
+SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
 {
-    this->setArchIntReg(SparcISA::ArgumentReg0 + i, val, tid);
+    TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
+            SparcISA::ArgumentReg0 + i);
+    this->setArchIntReg(idx, val, tid);
 }
 
 template <class Impl>
 void
 SparcO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
 {
-    // check for error condition.  SPARC syscall convention is to
-    // indicate success/failure in reg the carry bit of the ccr
-    // and put the return value itself in the standard return value reg ().
-    if (return_value.successful()) {
-        // no error, clear XCC.C
-        this->setMiscReg(SparcISA::MISCREG_CCR,
-                this->readMiscReg(SparcISA::MISCREG_CCR, tid) & 0xEE, tid);
-        this->setArchIntReg(SparcISA::ReturnValueReg,
-                return_value.value(), tid);
-    } else {
-        // got an error, set XCC.C
-        this->setMiscReg(SparcISA::MISCREG_CCR,
-                this->readMiscReg(SparcISA::MISCREG_CCR, tid) | 0x11, tid);
-        this->setArchIntReg(SparcISA::ReturnValueReg,
-                return_value.value(), tid);
-    }
+    TheISA::setSyscallReturn(return_value, this->tcBase(tid));
 }
 #endif