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-rwxr-xr-xsrc/cpu/o3/thread_context.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index b10305d5d..a3f1ce58f 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -226,6 +226,9 @@ class O3ThreadContext : public ThreadContext
* write might have as defined by the architecture. */
virtual void setMiscReg(int misc_reg, const MiscReg &val);
+ virtual int flattenIntIndex(int reg);
+ virtual int flattenFloatIndex(int reg);
+
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.
virtual unsigned readStCondFailures()