summaryrefslogtreecommitdiff
path: root/src/cpu/o3/thread_context.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/o3/thread_context.hh')
-rwxr-xr-xsrc/cpu/o3/thread_context.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 9ca02b9f3..4556c5e22 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -201,15 +201,15 @@ class O3ThreadContext : public ThreadContext
/** Reads a misc. register, including any side-effects the
* read might have as defined by the architecture. */
- virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
- { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); }
+ virtual MiscReg readMiscRegWithEffect(int misc_reg)
+ { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
/** Sets a misc. register. */
- virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
+ virtual void setMiscReg(int misc_reg, const MiscReg &val);
/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
- virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+ virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.