diff options
Diffstat (limited to 'src/cpu/o3/thread_context.hh')
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 9ca02b9f3..daee2fc7d 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -83,7 +83,7 @@ class O3ThreadContext : public ThreadContext virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } /** Returns a pointer to this thread's kernel statistics. */ - virtual Kernel::Statistics *getKernelStats() + virtual TheISA::Kernel::Statistics *getKernelStats() { return thread->kernelStats; } virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } @@ -201,15 +201,15 @@ class O3ThreadContext : public ThreadContext /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); } + virtual MiscReg readMiscRegWithEffect(int misc_reg) + { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); } /** Sets a misc. register. */ - virtual Fault setMiscReg(int misc_reg, const MiscReg &val); + virtual void setMiscReg(int misc_reg, const MiscReg &val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val); /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. |