diff options
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
-rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 34 |
1 files changed, 24 insertions, 10 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index bce334dc4..6527f5d06 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -272,7 +272,7 @@ template <class Impl> uint64_t O3ThreadContext<Impl>::readIntReg(int reg_idx) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); return cpu->readArchIntReg(reg_idx, thread->threadId()); } @@ -280,7 +280,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); switch(width) { case 32: return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); @@ -296,7 +296,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); } @@ -305,7 +305,7 @@ TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } @@ -313,7 +313,7 @@ template <class Impl> TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } @@ -321,7 +321,7 @@ template <class Impl> void O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); cpu->setArchIntReg(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -334,7 +334,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); switch(width) { case 32: cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); @@ -354,7 +354,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); if (!thread->trapPending && !thread->inSyscall) { @@ -368,7 +368,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -381,7 +381,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -439,6 +439,20 @@ O3ThreadContext<Impl>::setNextMicroPC(uint64_t val) } template <class Impl> +int +O3ThreadContext<Impl>::flattenIntIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenIntIndex(reg); +} + +template <class Impl> +int +O3ThreadContext<Impl>::flattenFloatIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenFloatIndex(reg); +} + +template <class Impl> void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { |