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-rw-r--r--src/cpu/o3/fetch_impl.hh5
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh4
2 files changed, 9 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 84f2c3b7e..3a41de721 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -30,6 +30,7 @@
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/exetrace.hh"
#include "cpu/o3/fetch.hh"
#include "mem/packet.hh"
@@ -289,6 +290,10 @@ DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
icachePort->setPeer(mem_dport);
mem_dport->setPeer(icachePort);
+ if (cpu->checker) {
+ cpu->checker->setIcachePort(icachePort);
+ }
+
// Fetch needs to start fetching instructions at the very beginning,
// so it must start up in active state.
switchToActive();
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 5398426e2..2679eb52b 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -186,6 +186,10 @@ LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
Port *mem_dport = mem->getPort("");
dcachePort->setPeer(mem_dport);
mem_dport->setPeer(dcachePort);
+
+ if (cpu->checker) {
+ cpu->checker->setDcachePort(dcachePort);
+ }
}
template<class Impl>