diff options
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 1 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 28 |
2 files changed, 17 insertions, 12 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index fbe5248f7..1c8b98f2e 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -1045,7 +1045,6 @@ LSQUnit<Impl>::read(const RequestPtr &req, " req=%#x\n", load_inst->seqNum, load_inst->postReq->getVaddr()); } - load_inst->needDeletePostReq(true); } else { load_inst->setExposeCompleted(); load_inst->needPostFetch(false); diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 164a768bb..56870b5a3 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1197,6 +1197,23 @@ LSQUnit<Impl>::exposeLoads() load_inst->postSreqHigh->getVaddr()); } + bool split = false; + if (TheISA::HasUnalignedMemAcc && sreqLow) { + split = true; + } else { + assert(req); + } + + if (load_inst->isL1HitLow() && (!split || load_inst->isL1HitHigh()) ) { + load_inst->setExposeCompleted(); + load_inst->setExposeSent(); + --loadsToVLD; + incrLdIdx(loadVLDIdx); + iewStage->instToCommit(load_inst); + iewStage->activityThisCycle(); + continue; + } + PacketPtr data_pkt = NULL; PacketPtr snd_data_pkt = NULL; @@ -1206,13 +1223,6 @@ LSQUnit<Impl>::exposeLoads() state->inst = load_inst; state->noWB = true; - bool split = false; - if (TheISA::HasUnalignedMemAcc && sreqLow) { - split = true; - } else { - assert(req); - } - bool onlyExpose = false; if (!split) { if (load_inst->needExposeOnly() || load_inst->isL1HitLow()){ @@ -1325,10 +1335,6 @@ LSQUnit<Impl>::exposeLoads() ++lsqCacheBlocked; break; } else { - // Here is to fix memory leakage - // it is ugly, but we have to do it now. - load_inst->needDeletePostReq(false); - // if all the packets we sent out is expose, // we assume the expose is alreay completed if (onlyExpose) { |