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-rw-r--r--src/cpu/o3/commit_impl.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f579305dc..c0946c16f 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -714,9 +714,9 @@ DefaultCommit<Impl>::handleInterrupt()
return;
}
- // Wait until the ROB is empty and all stores have drained in
- // order to enter the interrupt.
- if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ // Wait until all in flight instructions are finished before enterring
+ // the interrupt.
+ if (cpu->instList.empty()) {
// Squash or record that I need to squash this cycle if
// an interrupt needed to be handled.
DPRINTF(Commit, "Interrupt detected.\n");